Lines Matching refs:RetVT
196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
201 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
204 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
207 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
210 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
215 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
224 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
225 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
226 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
235 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
239 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
242 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
244 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
248 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
250 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
252 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
255 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
256 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
258 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
260 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
262 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
266 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
270 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
284 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
1158 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS, in emitAddSub() argument
1163 switch (RetVT.SimpleTy) { in emitAddSub()
1181 MVT SrcVT = RetVT; in emitAddSub()
1182 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32); in emitAddSub()
1208 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1214 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1217 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1221 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1237 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1245 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1265 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1290 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1308 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1312 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr() argument
1322 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rr()
1331 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rr()
1350 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri() argument
1355 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_ri()
1373 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_ri()
1395 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs() argument
1405 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rs()
1409 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1418 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rs()
1438 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx() argument
1448 if (RetVT != MVT::i32 && RetVT != MVT::i64) in emitAddSub_rx()
1460 bool Is64Bit = RetVT == MVT::i64; in emitAddSub_rx()
1505 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, in emitICmp() argument
1507 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false, in emitICmp()
1511 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitICmp_ri() argument
1513 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm, in emitICmp_ri()
1517 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) { in emitFCmp() argument
1518 if (RetVT != MVT::f32 && RetVT != MVT::f64) in emitFCmp()
1534 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp()
1545 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp()
1552 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, in emitAdd() argument
1554 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult, in emitAdd()
1582 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS, in emitSub() argument
1584 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult, in emitSub()
1588 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr() argument
1591 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rr()
1595 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs() argument
1600 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rs()
1605 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, in emitLogicalOp() argument
1630 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1652 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1668 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1680 MVT VT = std::max(MVT::i32, RetVT.SimpleTy); in emitLogicalOp()
1682 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp()
1683 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp()
1689 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_ri() argument
1702 switch (RetVT.SimpleTy) { in emitLogicalOp_ri()
1728 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) { in emitLogicalOp_ri()
1729 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_ri()
1735 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, in emitLogicalOp_rs() argument
1748 if (ShiftImm >= RetVT.getSizeInBits()) in emitLogicalOp_rs()
1753 switch (RetVT.SimpleTy) { in emitLogicalOp_rs()
1771 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) { in emitLogicalOp_rs()
1772 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; in emitLogicalOp_rs()
1778 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitAnd_ri() argument
1780 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm); in emitAnd_ri()
1783 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr, in emitLoad() argument
1859 bool IsRet64Bit = RetVT == MVT::i64; in emitLoad()
1908 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) { in emitLoad()
2006 MVT RetVT = VT; in selectLoad() local
2010 if (isTypeSupported(ZE->getType(), RetVT)) in selectLoad()
2013 RetVT = VT; in selectLoad()
2015 if (isTypeSupported(SE->getType(), RetVT)) in selectLoad()
2018 RetVT = VT; in selectLoad()
2024 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I)); in selectLoad()
2047 if (RetVT == MVT::i64 && VT <= MVT::i32) { in selectLoad()
3150 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, in finishCall() argument
3160 if (RetVT != MVT::isVoid) { in finishCall()
3163 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC)); in finishCall()
3222 MVT RetVT; in fastLowerCall() local
3224 RetVT = MVT::isVoid; in fastLowerCall()
3225 else if (!isTypeLegal(CLI.RetTy, RetVT)) in fastLowerCall()
3323 return finishCall(CLI, RetVT, NumBytes); in fastLowerCall()
3398 MVT RetVT; in foldXALUIntrinsic() local
3402 if (!isTypeLegal(RetTy, RetVT)) in foldXALUIntrinsic()
3405 if (RetVT != MVT::i32 && RetVT != MVT::i64) in foldXALUIntrinsic()
3576 MVT RetVT; in fastLowerIntrinsicCall() local
3577 if (!isTypeLegal(II->getType(), RetVT)) in fastLowerIntrinsicCall()
3580 if (RetVT != MVT::f32 && RetVT != MVT::f64) in fastLowerIntrinsicCall()
3589 bool Is64Bit = RetVT == MVT::f64; in fastLowerIntrinsicCall()
4039 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitMul_rr() argument
4042 switch (RetVT.SimpleTy) { in emitMul_rr()
4047 RetVT = MVT::i32; in emitMul_rr()
4054 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitMul_rr()
4059 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitSMULL_rr() argument
4061 if (RetVT != MVT::i64) in emitSMULL_rr()
4069 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill, in emitUMULL_rr() argument
4071 if (RetVT != MVT::i64) in emitUMULL_rr()
4079 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSL_rr() argument
4084 switch (RetVT.SimpleTy) { in emitLSL_rr()
4093 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSL_rr()
4105 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
4108 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4113 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSL_ri()
4114 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSL_ri()
4116 bool Is64Bit = (RetVT == MVT::i64); in emitLSL_ri()
4118 unsigned DstBits = RetVT.getSizeInBits(); in emitLSL_ri()
4125 if (RetVT == SrcVT) { in emitLSL_ri()
4132 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4172 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4185 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitLSR_rr() argument
4190 switch (RetVT.SimpleTy) { in emitLSR_rr()
4199 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitLSR_rr()
4212 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4215 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
4220 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitLSR_ri()
4221 RetVT == MVT::i64) && "Unexpected return value type."); in emitLSR_ri()
4223 bool Is64Bit = (RetVT == MVT::i64); in emitLSR_ri()
4225 unsigned DstBits = RetVT.getSizeInBits(); in emitLSR_ri()
4232 if (RetVT == SrcVT) { in emitLSR_ri()
4239 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4272 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitLSR_ri()
4277 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4281 SrcVT = RetVT; in emitLSR_ri()
4293 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4306 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill, in emitASR_rr() argument
4311 switch (RetVT.SimpleTy) { in emitASR_rr()
4320 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass; in emitASR_rr()
4322 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*isZExt=*/false); in emitASR_rr()
4333 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4336 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitASR_ri()
4341 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 || in emitASR_ri()
4342 RetVT == MVT::i64) && "Unexpected return value type."); in emitASR_ri()
4344 bool Is64Bit = (RetVT == MVT::i64); in emitASR_ri()
4346 unsigned DstBits = RetVT.getSizeInBits(); in emitASR_ri()
4353 if (RetVT == SrcVT) { in emitASR_ri()
4360 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4393 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT); in emitASR_ri()
4402 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4524 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT, in optimizeIntExtLoad() argument
4553 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4581 MVT RetVT; in selectIntExt() local
4583 if (!isTypeSupported(I->getType(), RetVT)) in selectIntExt()
4590 if (optimizeIntExtLoad(I, RetVT, SrcVT)) in selectIntExt()
4602 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4624 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4752 MVT RetVT; in selectShift() local
4753 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true)) in selectShift()
4756 if (RetVT.isVector()) in selectShift()
4762 MVT SrcVT = RetVT; in selectShift()
4793 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4796 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4799 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4823 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4826 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4829 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill); in selectShift()
4841 MVT RetVT, SrcVT; in selectBitCast() local
4845 if (!isTypeLegal(I->getType(), RetVT)) in selectBitCast()
4849 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4851 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4853 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4855 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()
4861 switch (RetVT.SimpleTy) { in selectBitCast()
4882 MVT RetVT; in selectFRem() local
4883 if (!isTypeLegal(I->getType(), RetVT)) in selectFRem()
4887 switch (RetVT.SimpleTy) { in selectFRem()