Lines Matching refs:SrcVT
196 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
233 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
264 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
268 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
272 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1181 MVT SrcVT = RetVT; in emitAddSub() local
1208 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1306 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
2879 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectFPToInt() local
2880 if (SrcVT == MVT::f128 || SrcVT == MVT::f16) in selectFPToInt()
2884 if (SrcVT == MVT::f64) { in selectFPToInt()
2919 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true); in selectIntToFP() local
2922 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) { in selectIntToFP()
2924 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP()
2931 if (SrcVT == MVT::i64) { in selectIntToFP()
3091 MVT SrcVT = ArgVT; in processCallArgs() local
3092 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
3101 MVT SrcVT = ArgVT; in processCallArgs() local
3102 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
3952 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc() local
3955 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 && in selectTrunc()
3956 SrcVT != MVT::i8) in selectTrunc()
3973 if (SrcVT == MVT::i64) { in selectTrunc()
4105 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSL_ri() argument
4108 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSL_ri()
4110 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSL_ri()
4111 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSL_ri()
4119 unsigned SrcBits = SrcVT.getSizeInBits(); in emitLSL_ri()
4125 if (RetVT == SrcVT) { in emitLSL_ri()
4132 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
4172 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSL_ri()
4212 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitLSR_ri() argument
4215 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitLSR_ri()
4217 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitLSR_ri()
4218 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitLSR_ri()
4226 unsigned SrcBits = SrcVT.getSizeInBits(); in emitLSR_ri()
4232 if (RetVT == SrcVT) { in emitLSR_ri()
4239 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4277 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4281 SrcVT = RetVT; in emitLSR_ri()
4282 SrcBits = SrcVT.getSizeInBits(); in emitLSR_ri()
4293 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitLSR_ri()
4333 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0, in emitASR_ri() argument
4336 assert(RetVT.SimpleTy >= SrcVT.SimpleTy && in emitASR_ri()
4338 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 || in emitASR_ri()
4339 SrcVT == MVT::i32 || SrcVT == MVT::i64) && in emitASR_ri()
4347 unsigned SrcBits = SrcVT.getSizeInBits(); in emitASR_ri()
4353 if (RetVT == SrcVT) { in emitASR_ri()
4360 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4402 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) { in emitASR_ri()
4415 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
4425 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && in emitIntExt()
4426 (SrcVT != MVT::i16) && (SrcVT != MVT::i32))) in emitIntExt()
4432 switch (SrcVT.SimpleTy) { in emitIntExt()
4525 MVT SrcVT) { in optimizeIntExtLoad() argument
4553 if (RetVT != MVT::i64 || SrcVT > MVT::i32) { in optimizeIntExtLoad()
4582 MVT SrcVT; in selectIntExt() local
4586 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT)) in selectIntExt()
4590 if (optimizeIntExtLoad(I, RetVT, SrcVT)) in selectIntExt()
4602 if (RetVT == MVT::i64 && SrcVT != MVT::i64) { in selectIntExt()
4624 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4696 MVT SrcVT = VT; in selectMul() local
4702 SrcVT = VT; in selectMul()
4711 SrcVT = VT; in selectMul()
4724 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4762 MVT SrcVT = RetVT; in selectShift() local
4769 SrcVT = TmpVT; in selectShift()
4778 SrcVT = TmpVT; in selectShift()
4793 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4796 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4799 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4841 MVT RetVT, SrcVT; in selectBitCast() local
4843 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT)) in selectBitCast()
4849 if (RetVT == MVT::f32 && SrcVT == MVT::i32) in selectBitCast()
4851 else if (RetVT == MVT::f64 && SrcVT == MVT::i64) in selectBitCast()
4853 else if (RetVT == MVT::i32 && SrcVT == MVT::f32) in selectBitCast()
4855 else if (RetVT == MVT::i64 && SrcVT == MVT::f64) in selectBitCast()