Lines Matching refs:constrainOperandRegClass

1139       constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));  in addLoadStoreOperands()
1141       constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));  in addLoadStoreOperands()
1342   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rr()
1343   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rr()
1387   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_ri()
1429   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rs()
1430   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rs()
1474   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rx()
1475   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rx()
2100   SrcReg = constrainOperandRegClass(II, SrcReg, 0);  in emitStoreRelease()
2101   AddrReg = constrainOperandRegClass(II, AddrReg, 1);  in emitStoreRelease()
2169   SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());  in emitStore()
2406   SrcReg = constrainOperandRegClass(II, SrcReg,  II.getNumDefs());  in emitCompareAndBranch()
2538     = constrainOperandRegClass(II, CondReg, II.getNumDefs());  in selectBranch()
2556   AddrReg = constrainOperandRegClass(II, AddrReg,  II.getNumDefs());  in selectIndirectBr()
2808     CondReg = constrainOperandRegClass(II, CondReg, 1);  in selectSelect()
3281       unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);  in fastLowerCall()
3308     CallReg = constrainOperandRegClass(II, CallReg, 0);  in fastLowerCall()
5116   const unsigned AddrReg = constrainOperandRegClass(  in selectAtomicCmpXchg()
5118   const unsigned DesiredReg = constrainOperandRegClass(  in selectAtomicCmpXchg()
5120   const unsigned NewReg = constrainOperandRegClass(  in selectAtomicCmpXchg()