Lines Matching refs:Offset64

9616                        int Offset128, int Offset64, bits<4> opcode> {
9665                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9670                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9675                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9682   defm : SIMDLdStAliases<BaseName, asm, "8b", Count, Offset64, 64>;
9683   defm : SIMDLdStAliases<BaseName, asm, "4h", Count, Offset64, 64>;
9684   defm : SIMDLdStAliases<BaseName, asm, "2s", Count, Offset64, 64>;
9689                        int Offset128, int Offset64, bits<4> opcode> {
9737                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9742                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9747                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9754   defm : SIMDLdStAliases<BaseName, asm, "8b", Count, Offset64, 64>;
9755   defm : SIMDLdStAliases<BaseName, asm, "4h", Count, Offset64, 64>;
9756   defm : SIMDLdStAliases<BaseName, asm, "2s", Count, Offset64, 64>;
9760                        int Offset128, int Offset64, bits<4> opcode>
9761   : BaseSIMDLdN<BaseName, Count, asm, veclist, Offset128, Offset64, opcode> {
9773                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9776   defm : SIMDLdStAliases<BaseName, asm, "1d", Count, Offset64, 64>;
9780                        int Offset128, int Offset64, bits<4> opcode>
9781   : BaseSIMDStN<BaseName, Count, asm, veclist, Offset128, Offset64, opcode> {
9793                             !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
9796   defm : SIMDLdStAliases<BaseName, asm, "1d", Count, Offset64, 64>;