Lines Matching refs:ZeroReg
2745 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
2760 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4045 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
4064 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
4074 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
4075 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
4135 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
4137 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
4790 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4795 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4802 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
4818 .addReg(ZeroReg) in genAlternativeCodeSequence()
4834 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
4838 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4844 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
4852 .addReg(ZeroReg) in genAlternativeCodeSequence()
4882 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4887 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4894 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
4909 .addReg(ZeroReg) in genAlternativeCodeSequence()