Lines Matching refs:MIRBuilder
56 IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in IncomingArgHandler()
58 : IncomingValueHandler(MIRBuilder, MRI, AssignFn), StackUsed(0) {} in IncomingArgHandler()
62 auto &MFI = MIRBuilder.getMF().getFrameInfo(); in getStackAddress()
64 MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI); in getStackAddress()
65 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); in getStackAddress()
75 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
80 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
81 MIRBuilder.buildTrunc(ValVReg, Copy); in assignValueToReg()
89 MachineFunction &MF = MIRBuilder.getMF(); in assignValueToAddress()
98 MIRBuilder.buildLoad(ValVReg, Addr, *MMO); in assignValueToAddress()
110 FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in FormalArgHandler()
112 : IncomingArgHandler(MIRBuilder, MRI, AssignFn) {} in FormalArgHandler()
115 MIRBuilder.getMRI()->addLiveIn(PhysReg); in markPhysRegUsed()
116 MIRBuilder.getMBB().addLiveIn(PhysReg); in markPhysRegUsed()
121 CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in CallReturnHandler()
123 : IncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {} in CallReturnHandler()
133 OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, in OutgoingArgHandler()
137 : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingArgHandler()
143 MachineFunction &MF = MIRBuilder.getMF(); in getStackAddress()
150 auto FIReg = MIRBuilder.buildFrameIndex(p0, FI); in getStackAddress()
156 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
158 auto OffsetReg = MIRBuilder.buildConstant(s64, Offset); in getStackAddress()
160 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); in getStackAddress()
170 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
175 MachineFunction &MF = MIRBuilder.getMF(); in assignValueToAddress()
178 MIRBuilder.buildStore(ValVReg, Addr, *MMO); in assignValueToAddress()
274 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder, in lowerReturn() argument
278 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR); in lowerReturn()
284 MachineFunction &MF = MIRBuilder.getMF(); in lowerReturn()
314 CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0); in lowerReturn()
341 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
343 MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0); in lowerReturn()
346 CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}) in lowerReturn()
353 auto Undef = MIRBuilder.buildUndef({OldLLT}); in lowerReturn()
355 MIRBuilder in lowerReturn()
365 MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg}).getReg(0); in lowerReturn()
377 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFn, AssignFn); in lowerReturn()
378 Success = handleAssignments(MIRBuilder, SplitArgs, Handler); in lowerReturn()
383 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
386 MIRBuilder.insertInstr(MIB); in lowerReturn()
393 static void handleMustTailForwardedRegisters(MachineIRBuilder &MIRBuilder, in handleMustTailForwardedRegisters() argument
395 MachineBasicBlock &MBB = MIRBuilder.getMBB(); in handleMustTailForwardedRegisters()
396 MachineFunction &MF = MIRBuilder.getMF(); in handleMustTailForwardedRegisters()
429 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
442 MachineIRBuilder &MIRBuilder, const Function &F, in lowerFormalArguments() argument
444 MachineFunction &MF = MIRBuilder.getMF(); in lowerFormalArguments()
445 MachineBasicBlock &MBB = MIRBuilder.getMBB(); in lowerFormalArguments()
463 MIRBuilder.setInstr(*MBB.begin()); in lowerFormalArguments()
469 FormalArgHandler Handler(MIRBuilder, MRI, AssignFn); in lowerFormalArguments()
470 if (!handleAssignments(MIRBuilder, SplitArgs, Handler)) in lowerFormalArguments()
486 auto &MFI = MIRBuilder.getMF().getFrameInfo(); in lowerFormalArguments()
514 handleMustTailForwardedRegisters(MIRBuilder, AssignFn); in lowerFormalArguments()
517 MIRBuilder.setMBB(MBB); in lowerFormalArguments()
686 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, in isEligibleForTailCallOptimization() argument
695 MachineFunction &MF = MIRBuilder.getMF(); in isEligibleForTailCallOptimization()
804 MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info, in lowerTailCall() argument
806 MachineFunction &MF = MIRBuilder.getMF(); in lowerTailCall()
831 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerTailCall()
834 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerTailCall()
891 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, in lowerTailCall()
893 if (!handleAssignments(MIRBuilder, OutArgs, Handler)) in lowerTailCall()
912 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
926 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP).addImm(NumBytes).addImm(0); in lowerTailCall()
930 MIRBuilder.insertInstr(MIB); in lowerTailCall()
945 bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, in lowerCall() argument
947 MachineFunction &MF = MIRBuilder.getMF(); in lowerCall()
967 isEligibleForTailCallOptimization(MIRBuilder, Info, InArgs, OutArgs); in lowerCall()
979 return lowerTailCall(MIRBuilder, Info, OutArgs); in lowerCall()
988 CallSeqStart = MIRBuilder.buildInstr(AArch64::ADJCALLSTACKDOWN); in lowerCall()
994 auto MIB = MIRBuilder.buildInstrNoInsert(Opc); in lowerCall()
1008 OutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed, in lowerCall()
1010 if (!handleAssignments(MIRBuilder, OutArgs, Handler)) in lowerCall()
1014 MIRBuilder.insertInstr(MIB); in lowerCall()
1030 CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn); in lowerCall()
1031 if (!handleAssignments(MIRBuilder, InArgs, Handler)) in lowerCall()
1037 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
1047 MIRBuilder.buildInstr(AArch64::ADJCALLSTACKUP) in lowerCall()