Lines Matching refs:v4s16
52 const LLT v4s16 = LLT::vector(4, 16); in AArch64LegalizerInfo() local
64 v8s8, v4s16, v2s32}; in AArch64LegalizerInfo()
108 .legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8, v8s8}) in AArch64LegalizerInfo()
134 {v4s16, v4s16}, in AArch64LegalizerInfo()
198 .legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16}); in AArch64LegalizerInfo()
281 {v4s16, p0, 64, 8}, in AArch64LegalizerInfo()
310 {v4s16, p0, 64, 8}, in AArch64LegalizerInfo()
347 {v4s16, v4s16}, in AArch64LegalizerInfo()
417 {{s16, s32}, {s16, s64}, {s32, s64}, {v4s16, v4s32}, {v2s32, v2s64}}) in AArch64LegalizerInfo()
421 {{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}}) in AArch64LegalizerInfo()
476 v8s16, v4s16, v2s16, v4s32, v2s32, v2s64, in AArch64LegalizerInfo()
590 return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 || in AArch64LegalizerInfo()
624 {v4s16, s16}, in AArch64LegalizerInfo()
642 {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32}) in AArch64LegalizerInfo()
668 .legalFor({{v4s32, v2s32}, {v8s16, v4s16}}); in AArch64LegalizerInfo()