Lines Matching refs:v8s16
51 const LLT v8s16 = LLT::vector(8, 16); in AArch64LegalizerInfo() local
60 v16s8, v8s16, v4s32, in AArch64LegalizerInfo()
108 .legalFor({s32, s64, v2s32, v4s32, v4s16, v8s16, v16s8, v8s8}) in AArch64LegalizerInfo()
135 {v8s16, v8s16}, in AArch64LegalizerInfo()
198 .legalFor({s16, s32, s64, v2s32, v4s32, v2s64, v2s16, v4s16, v8s16}); in AArch64LegalizerInfo()
282 {v8s16, p0, 128, 8}, in AArch64LegalizerInfo()
311 {v8s16, p0, 128, 8}, in AArch64LegalizerInfo()
348 {v8s16, v8s16}, in AArch64LegalizerInfo()
476 v8s16, v4s16, v2s16, v4s32, v2s32, v2s64, in AArch64LegalizerInfo()
590 return VecTy == v2s16 || VecTy == v4s16 || VecTy == v8s16 || in AArch64LegalizerInfo()
619 .legalIf(typeInSet(0, {v8s16, v2s32, v4s32, v2s64})); in AArch64LegalizerInfo()
625 {v8s16, s16}, in AArch64LegalizerInfo()
642 {s32, s64, v8s8, v16s8, v4s16, v8s16, v2s32, v4s32}) in AArch64LegalizerInfo()
653 for (auto &Ty : {v2s32, v4s32, v2s64, v2p0, v16s8, v8s16}) { in AArch64LegalizerInfo()
668 .legalFor({{v4s32, v2s32}, {v8s16, v4s16}}); in AArch64LegalizerInfo()
689 .legalFor({{s8, v16s8}, {s16, v8s16}, {s32, v4s32}, {s64, v2s64}}) in AArch64LegalizerInfo()