48       return MIRBuilder.buildAnyExt(LLT::scalar(32), ValVReg).getReg(0);  in extendRegisterMin32()
82       auto ToSGPR = MIRBuilder.buildIntrinsic(Intrinsic::amdgcn_readfirstlane,  in assignValueToReg()
88     MIRBuilder.buildCopy(PhysReg, ExtReg);  in assignValueToReg()
110     auto &MFI = MIRBuilder.getMF().getFrameInfo();  in getStackAddress()
112     MPO = MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);  in getStackAddress()
113     auto AddrReg = MIRBuilder.buildFrameIndex(  in getStackAddress()
126       auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);  in assignValueToReg()
127       MIRBuilder.buildTrunc(ValVReg, Copy);  in assignValueToReg()
135       auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);  in assignValueToReg()
136       MIRBuilder.buildTrunc(ValVReg, Copy);  in assignValueToReg()
140       MIRBuilder.buildCopy(ValVReg, PhysReg);  in assignValueToReg()
147     MachineFunction &MF = MIRBuilder.getMF();  in assignValueToAddress()
157     MIRBuilder.buildLoad(ValVReg, Addr, *MMO);  in assignValueToAddress()
172     MIRBuilder.getMBB().addLiveIn(PhysReg);  in markPhysRegUsed()
177   CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,  in CallReturnHandler()
179       : AMDGPUIncomingArgHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}  in CallReturnHandler()
201   AMDGPUOutgoingArgHandler(MachineIRBuilder &MIRBuilder,  in AMDGPUOutgoingArgHandler()
205       : AMDGPUValueHandler(false, MIRBuilder, MRI, AssignFn), MIB(MIB),  in AMDGPUOutgoingArgHandler()
211     MachineFunction &MF = MIRBuilder.getMF();  in getStackAddress()
222       SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0);  in getStackAddress()
224     auto OffsetReg = MIRBuilder.buildConstant(S32, Offset);  in getStackAddress()
226     auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg);  in getStackAddress()
235     MIRBuilder.buildCopy(PhysReg, ExtReg);  in assignValueToReg()
240     MachineFunction &MF = MIRBuilder.getMF();  in assignValueToAddress()
247     MIRBuilder.buildStore(ValVReg, Addr, *MMO);  in assignValueToAddress()
953 bool AMDGPUCallLowering::passSpecialInputs(MachineIRBuilder &MIRBuilder,  in passSpecialInputs()  argument
957   MachineFunction &MF = MIRBuilder.getMF();  in passSpecialInputs()
1004       LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy);  in passSpecialInputs()
1007       LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder);  in passSpecialInputs()
1054     LI->loadInputValue(InputReg, MIRBuilder, IncomingArgX,  in passSpecialInputs()
1060     LI->loadInputValue(Y, MIRBuilder, IncomingArgY, std::get<1>(WorkitemIDY),  in passSpecialInputs()
1063     Y = MIRBuilder.buildShl(S32, Y, MIRBuilder.buildConstant(S32, 10)).getReg(0);  in passSpecialInputs()
1064     InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y;  in passSpecialInputs()
1069     LI->loadInputValue(Z, MIRBuilder, IncomingArgZ, std::get<1>(WorkitemIDZ),  in passSpecialInputs()
1072     Z = MIRBuilder.buildShl(S32, Z, MIRBuilder.buildConstant(S32, 20)).getReg(0);  in passSpecialInputs()
1073     InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z;  in passSpecialInputs()
1084     LI->loadInputValue(InputReg, MIRBuilder, &IncomingArg,  in passSpecialInputs()
1114                                   MachineIRBuilder &MIRBuilder,  in addCallTargetOperands()  argument
1123     auto Ptr = MIRBuilder.buildGlobalValue(  in addCallTargetOperands()
1133 bool AMDGPUCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,  in lowerCall()  argument
1140   MachineFunction &MF = MIRBuilder.getMF();  in lowerCall()
1166       MIRBuilder, OrigArg, OutArgs, DL, Info.CallConv, true,  in lowerCall()
1171         unpackRegsToOrigType(MIRBuilder, Regs, SrcReg, OrigArg, LLTy, PartLLT);  in lowerCall()
1190   MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKUP)  in lowerCall()
1198   auto MIB = MIRBuilder.buildInstrNoInsert(Opc);  in lowerCall()
1201   if (!addCallTargetOperands(MIB, MIRBuilder, Info))  in lowerCall()
1218     if (!passSpecialInputs(MIRBuilder, CCInfo, ImplicitArgRegs, Info))  in lowerCall()
1224   AMDGPUOutgoingArgHandler Handler(MIRBuilder, MRI, MIB, AssignFnFixed,  in lowerCall()
1226   if (!handleAssignments(CCInfo, ArgLocs, MIRBuilder, OutArgs, Handler))  in lowerCall()
1234     auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::vector(4, 32),  in lowerCall()
1236     MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);  in lowerCall()
1241     MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);  in lowerCall()
1261   auto OrigInsertPt = MIRBuilder.getInsertPt();  in lowerCall()
1264   MIRBuilder.insertInstr(MIB);  in lowerCall()
1268     MIRBuilder.buildInstr(AMDGPU::ADJCALLSTACKDOWN);  in lowerCall()
1273       MIRBuilder, Info.OrigRet, InArgs, DL, Info.CallConv, false,  in lowerCall()
1277         packSplitRegsToOrigType(MIRBuilder,  Info.OrigRet.Regs[VTSplitIdx],  in lowerCall()
1284   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), CallSeqEnd);  in lowerCall()
1292     CallReturnHandler Handler(MIRBuilder, MRI, MIB, RetAssignFn);  in lowerCall()
1293     if (!handleAssignments(MIRBuilder, InArgs, Handler))  in lowerCall()
1302   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), OrigInsertPt);  in lowerCall()