Lines Matching refs:RBI
56 const GCNSubtarget &STI, const AMDGPURegisterBankInfo &RBI, in AMDGPUInstructionSelector() argument
59 TRI(*STI.getRegisterInfo()), RBI(RBI), TM(TM), in AMDGPUInstructionSelector()
119 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
120 RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI); in constrainCopyLikeIntrin()
139 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
144 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
173 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
187 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI); in selectCOPY()
227 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
280 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
282 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR()
296 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_AND_OR_XOR()
309 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB()
321 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB()
329 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_ADD_SUB()
342 return constrainSelectedInstRegOperands(*Add, TII, TRI, RBI); in selectG_ADD_SUB()
382 if (!constrainSelectedInstRegOperands(*Addc, TII, TRI, RBI)) in selectG_ADD_SUB()
393 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI)) in selectG_ADD_SUB()
419 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_UADDO_USUBO_UADDE_USUBE()
442 if (!RBI.constrainGenericRegister(Dst0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE()
443 !RBI.constrainGenericRegister(Src0Reg, AMDGPU::SReg_32RegClass, *MRI) || in selectG_UADDO_USUBO_UADDE_USUBE()
444 !RBI.constrainGenericRegister(Src1Reg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_UADDO_USUBO_UADDE_USUBE()
448 !RBI.constrainGenericRegister(I.getOperand(4).getReg(), in selectG_UADDO_USUBO_UADDE_USUBE()
478 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT()
481 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT()
492 SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I, in selectG_EXTRACT()
513 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_MERGE_VALUES()
530 if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI)) in selectG_MERGE_VALUES()
534 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
555 const RegisterBank *SrcBank = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_UNMERGE_VALUES()
559 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectG_UNMERGE_VALUES()
573 if (!SrcRC || !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI)) in selectG_UNMERGE_VALUES()
578 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI)) in selectG_UNMERGE_VALUES()
598 const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI); in selectG_BUILD_VECTOR_TRUNC()
620 return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI); in selectG_BUILD_VECTOR_TRUNC()
630 return RBI.constrainGenericRegister(Dst, AMDGPU::SReg_32RegClass, *MRI) && in selectG_BUILD_VECTOR_TRUNC()
631 RBI.constrainGenericRegister(Src0, AMDGPU::SReg_32RegClass, *MRI); in selectG_BUILD_VECTOR_TRUNC()
668 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC()
672 return constrainSelectedInstRegOperands(MI, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC()
686 (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) { in selectG_IMPLICIT_DEF()
719 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_INSERT()
725 const RegisterBank *Src0Bank = RBI.getRegBank(Src0Reg, *MRI, TRI); in selectG_INSERT()
726 const RegisterBank *Src1Bank = RBI.getRegBank(Src1Reg, *MRI, TRI); in selectG_INSERT()
738 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_INSERT()
739 !RBI.constrainGenericRegister(Src0Reg, *Src0RC, *MRI) || in selectG_INSERT()
740 !RBI.constrainGenericRegister(Src1Reg, *Src1RC, *MRI)) in selectG_INSERT()
760 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI) || in selectInterpP1F16()
761 !RBI.constrainGenericRegister(Dst, AMDGPU::VGPR_32RegClass, *MRI) || in selectInterpP1F16()
762 !RBI.constrainGenericRegister(Src0, AMDGPU::VGPR_32RegClass, *MRI)) in selectInterpP1F16()
841 RBI.constrainGenericRegister(LaneSelect, AMDGPU::SReg_32_XM0RegClass, *MRI); in selectWritelane()
852 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectWritelane()
893 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDivScale()
1026 unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI); in selectG_ICMP()
1041 constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI) && in selectG_ICMP()
1042 RBI.constrainGenericRegister(CCReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_ICMP()
1055 RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), in selectG_ICMP()
1057 bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); in selectG_ICMP()
1073 unsigned Size = RBI.getSizeInBits(SrcReg, *MRI, TRI); in selectIntrinsicIcmp()
1083 RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(), *TRI.getBoolRC(), in selectIntrinsicIcmp()
1085 bool Ret = constrainSelectedInstRegOperands(*ICmp, TII, TRI, RBI); in selectIntrinsicIcmp()
1124 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectRelocConstant()
1127 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectRelocConstant()
1151 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize()
1171 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGroupStaticSize()
1186 !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectReturnAddress()
1281 if (!RBI.constrainGenericRegister(M0Val, AMDGPU::SReg_32RegClass, *MRI)) in selectDSOrderedIntrinsic()
1284 bool Ret = constrainSelectedInstRegOperands(*DS, TII, TRI, RBI); in selectDSOrderedIntrinsic()
1319 const RegisterBank *OffsetRB = RBI.getRegBank(BaseOffset, *MRI, TRI); in selectDSGWSIntrinsic()
1358 if (!RBI.constrainGenericRegister(BaseOffset, AMDGPU::VGPR_32RegClass, *MRI)) in selectDSGWSIntrinsic()
1364 if (!RBI.constrainGenericRegister(BaseOffset, in selectDSGWSIntrinsic()
1386 if (!RBI.constrainGenericRegister(VSrc, AMDGPU::VGPR_32RegClass, *MRI)) in selectDSGWSIntrinsic()
1418 if (!RBI.constrainGenericRegister(PtrBase, AMDGPU::SReg_32RegClass, *MRI)) in selectDSAppendConsume()
1426 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectDSAppendConsume()
1717 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectImageIntrinsic()
1758 unsigned Size = RBI.getSizeInBits(DstReg, *MRI, TRI); in selectG_SELECT()
1777 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) | in selectG_SELECT()
1778 constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); in selectG_SELECT()
1795 bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); in selectG_SELECT()
1828 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_TRUNC()
1835 DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_TRUNC()
1852 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) || in selectG_TRUNC()
1853 !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) { in selectG_TRUNC()
1930 if (!RBI.constrainGenericRegister(SrcReg, *SrcWithSubRC, *MRI)) in selectG_TRUNC()
1958 return &RBI.getRegBankFromRegClass(*RC, LLT()); in getArtifactRegBank()
1988 const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_SZA_EXT()
2001 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) && in selectG_SZA_EXT()
2002 RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI); in selectG_SZA_EXT()
2016 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in selectG_SZA_EXT()
2026 return constrainSelectedInstRegOperands(*ExtI, TII, TRI, RBI); in selectG_SZA_EXT()
2032 if (!RBI.constrainGenericRegister(SrcReg, SrcRC, *MRI)) in selectG_SZA_EXT()
2041 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_SZA_EXT()
2066 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_64RegClass, *MRI); in selectG_SZA_EXT()
2081 return RBI.constrainGenericRegister(DstReg, AMDGPU::SReg_32RegClass, *MRI); in selectG_SZA_EXT()
2103 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_CONSTANT()
2122 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in selectG_CONSTANT()
2159 return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI); in selectG_CONSTANT()
2175 const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI); in selectG_FNEG()
2185 if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) || in selectG_FNEG()
2186 !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI)) in selectG_FNEG()
2220 const RegisterBank *DstRB = RBI.getRegBank(Dst, *MRI, TRI); in selectG_FABS()
2233 if (!RBI.constrainGenericRegister(Src, AMDGPU::SReg_64RegClass, *MRI) || in selectG_FABS()
2234 !RBI.constrainGenericRegister(Dst, AMDGPU::SReg_64RegClass, *MRI)) in selectG_FABS()
2286 const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI); in getAddrModeInfo()
2298 return RBI.getRegBank(Reg, *MRI, TRI)->getID() == AMDGPU::SGPRRegBankID; in isSGPR()
2407 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_AMDGPU_ATOMIC_CMPXCHG()
2458 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_GLOBAL_VALUE()
2464 return RBI.constrainGenericRegister( in selectG_GLOBAL_VALUE()
2475 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_PTRMASK()
2476 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_PTRMASK()
2477 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2493 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_PTRMASK()
2494 !RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) || in selectG_PTRMASK()
2495 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
2603 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT()
2604 const RegisterBank *SrcRB = RBI.getRegBank(SrcReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT()
2605 const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI); in selectG_EXTRACT_VECTOR_ELT()
2618 if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) || in selectG_EXTRACT_VECTOR_ELT()
2619 !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) || in selectG_EXTRACT_VECTOR_ELT()
2620 !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_EXTRACT_VECTOR_ELT()
2683 const RegisterBank *VecRB = RBI.getRegBank(VecReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2684 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2685 const RegisterBank *IdxRB = RBI.getRegBank(IdxReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2699 if (!RBI.constrainGenericRegister(VecReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2700 !RBI.constrainGenericRegister(DstReg, *VecRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2701 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2702 !RBI.constrainGenericRegister(IdxReg, AMDGPU::SReg_32RegClass, *MRI)) in selectG_INSERT_VECTOR_ELT()
2795 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_SHUFFLE_VECTOR()
2805 return RBI.constrainGenericRegister(DstReg, RC, *MRI); in selectG_SHUFFLE_VECTOR()
2812 if (!RBI.constrainGenericRegister(DstReg, RC, *MRI) || in selectG_SHUFFLE_VECTOR()
2813 !RBI.constrainGenericRegister(SrcVec, RC, *MRI)) in selectG_SHUFFLE_VECTOR()
3017 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectGlobalAtomicFaddIntrinsic()
3184 RBI.getRegBank(Src, *MRI, TRI)->getID() != AMDGPU::VGPRRegBankID) { in selectVOP3ModsImpl()
3969 const RegisterBank *N0Bank = RBI.getRegBank(Addr.N0, *MRI, TRI); in shouldUseAddr64()
4010 if (RBI.getRegBank(N2, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID) { in selectMUBUFAddr64Impl()
4012 if (RBI.getRegBank(N3, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID) { in selectMUBUFAddr64Impl()
4025 } else if (RBI.getRegBank(N0, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID) { in selectMUBUFAddr64Impl()