Lines Matching refs:AMDGPU
121 if (Opc == AMDGPU::G_ANYEXT || Opc == AMDGPU::G_ZEXT || in applyBank()
122 Opc == AMDGPU::G_SEXT) { in applyBank()
129 if (SrcBank == &AMDGPU::VCCRegBank) { in applyBank()
133 assert(NewBank == &AMDGPU::VGPRRegBank); in applyBank()
138 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
152 if (Opc == AMDGPU::G_TRUNC) { in applyBank()
155 assert(DstBank != &AMDGPU::VCCRegBank); in applyBank()
170 assert(NewBank == &AMDGPU::VGPRRegBank && in applyBank()
172 assert((MI.getOpcode() != AMDGPU::G_TRUNC && in applyBank()
173 MI.getOpcode() != AMDGPU::G_ANYEXT) && in applyBank()
175 RB = &AMDGPU::VCCRegBank; in applyBank()
204 assert(&getRegBank(AMDGPU::SGPRRegBankID) == &AMDGPU::SGPRRegBank && in AMDGPURegisterBankInfo()
205 &getRegBank(AMDGPU::VGPRRegBankID) == &AMDGPU::VGPRRegBank && in AMDGPURegisterBankInfo()
206 &getRegBank(AMDGPU::AGPRRegBankID) == &AMDGPU::AGPRRegBank); in AMDGPURegisterBankInfo()
215 return BankID == AMDGPU::VGPRRegBankID || BankID == AMDGPU::AGPRRegBankID; in isVectorRegisterBank()
222 if (Dst.getID() == AMDGPU::SGPRRegBankID && in copyCost()
223 (isVectorRegisterBank(Src) || Src.getID() == AMDGPU::VCCRegBankID)) { in copyCost()
235 (Dst.getID() == AMDGPU::SGPRRegBankID) && in copyCost()
237 Src.getID() == AMDGPU::SGPRRegBankID || in copyCost()
238 Src.getID() == AMDGPU::VCCRegBankID)) in copyCost()
242 if (Dst.getID() == AMDGPU::AGPRRegBankID && in copyCost()
243 Src.getID() == AMDGPU::AGPRRegBankID) in copyCost()
277 if (&RC == &AMDGPU::SReg_1RegClass) in getRegBankFromRegClass()
278 return AMDGPU::VCCRegBank; in getRegBankFromRegClass()
287 return AMDGPU::SGPRRegBank; in getRegBankFromRegClass()
289 return Ty == LLT::scalar(1) ? AMDGPU::VCCRegBank : AMDGPU::SGPRRegBank; in getRegBankFromRegClass()
292 return TRI->isAGPRClass(&RC) ? AMDGPU::AGPRRegBank : AMDGPU::VGPRRegBank; in getRegBankFromRegClass()
314 Operands[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SizeI); in addMappingFromTable()
322 Operands[OpIdx] = AMDGPU::getValueMapping(Entry.RegBanks[I], Sizes[I]); in addMappingFromTable()
340 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsic()
343 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsic()
352 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
355 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
358 …{ { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
361 …{ { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, … in getInstrAlternativeMappingsIntrinsic()
381 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
384 { { AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 300 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
387 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID }, 1000 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
390 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1500 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
402 { { AMDGPU::VGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
405 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 2 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
416 { { AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappingsIntrinsicWSideEffects()
419 { { AMDGPU::VGPRRegBankID }, 3 } in getInstrAlternativeMappingsIntrinsicWSideEffects()
472 { { AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
473 { { AMDGPU::SGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
474 { { AMDGPU::VCCRegBankID }, 1 } in getInstrAlternativeMappings()
486 { { AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
487 { { AMDGPU::SGPRRegBankID }, 1 } in getInstrAlternativeMappings()
501 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32), in getInstrAlternativeMappings()
502 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32), in getInstrAlternativeMappings()
503 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32)}), in getInstrAlternativeMappings()
509 {AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size), in getInstrAlternativeMappings()
510 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size), in getInstrAlternativeMappings()
511 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size)}), in getInstrAlternativeMappings()
522 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
523 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
524 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}), in getInstrAlternativeMappings()
530 {AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
531 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
532 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}), in getInstrAlternativeMappings()
550 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
551 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize)}), in getInstrAlternativeMappings()
559 {AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
560 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize)}), in getInstrAlternativeMappings()
576 getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
577 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), in getInstrAlternativeMappings()
578 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
579 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}), in getInstrAlternativeMappings()
584 getOperandsMapping({AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
585 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), in getInstrAlternativeMappings()
586 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
587 AMDGPU::getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size)}), in getInstrAlternativeMappings()
598 { { AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID, AMDGPU::VGPRRegBankID }, 1 }, in getInstrAlternativeMappings()
602 { { AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID, AMDGPU::SGPRRegBankID }, 3 } in getInstrAlternativeMappings()
615 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
616 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), in getInstrAlternativeMappings()
617 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
618 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size), in getInstrAlternativeMappings()
619 AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1)}), in getInstrAlternativeMappings()
624 getOperandsMapping({AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
625 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), in getInstrAlternativeMappings()
626 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
627 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size), in getInstrAlternativeMappings()
628 AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1)}), in getInstrAlternativeMappings()
633 case AMDGPU::G_BRCOND: { in getInstrAlternativeMappings()
639 {AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 1), nullptr}), in getInstrAlternativeMappings()
645 {AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1), nullptr }), in getInstrAlternativeMappings()
650 case AMDGPU::G_INTRINSIC: in getInstrAlternativeMappings()
652 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: in getInstrAlternativeMappings()
676 B.buildInstr(AMDGPU::G_UNMERGE_VALUES) in split64BitValueForMapping()
737 AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in executeInWaterfallLoop()
739 AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in executeInWaterfallLoop()
741 AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term; in executeInWaterfallLoop()
743 AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in executeInWaterfallLoop()
745 AMDGPU::EXEC_LO : AMDGPU::EXEC; in executeInWaterfallLoop()
857 if (OpBank != &AMDGPU::VGPRRegBank) { in executeInWaterfallLoop()
861 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
871 = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
874 constrainGenericRegister(OpReg, AMDGPU::VGPR_32RegClass, MRI); in executeInWaterfallLoop()
876 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), in executeInWaterfallLoop()
881 bool First = CondReg == AMDGPU::NoRegister; in executeInWaterfallLoop()
886 B.buildInstr(AMDGPU::V_CMP_EQ_U32_e64) in executeInWaterfallLoop()
912 unsigned CmpOp = OpSize % 64 == 0 ? AMDGPU::V_CMP_EQ_U64_e64 in executeInWaterfallLoop()
913 : AMDGPU::V_CMP_EQ_U32_e64; in executeInWaterfallLoop()
933 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass); in executeInWaterfallLoop()
934 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
935 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
938 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), in executeInWaterfallLoop()
940 .addReg(UnmergePiece, 0, AMDGPU::sub0); in executeInWaterfallLoop()
943 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), in executeInWaterfallLoop()
945 .addReg(UnmergePiece, 0, AMDGPU::sub1); in executeInWaterfallLoop()
952 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass); in executeInWaterfallLoop()
965 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass); in executeInWaterfallLoop()
966 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
969 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), in executeInWaterfallLoop()
976 bool First = CondReg == AMDGPU::NoRegister; in executeInWaterfallLoop()
1007 MRI.setRegBank(Op.getReg(), AMDGPU::SGPRRegBank); in executeInWaterfallLoop()
1034 B.buildInstr(AMDGPU::S_CBRANCH_EXECNZ) in executeInWaterfallLoop()
1065 if (OpBank->getID() != AMDGPU::SGPRRegBankID) in collectWaterfallOperands()
1100 if (Bank == &AMDGPU::SGPRRegBank) in constrainOpWithReadfirstlane()
1106 if (Bank != &AMDGPU::VGPRRegBank) { in constrainOpWithReadfirstlane()
1109 MRI.setRegBank(Reg, AMDGPU::VGPRRegBank); in constrainOpWithReadfirstlane()
1112 Register SGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in constrainOpWithReadfirstlane()
1113 B.buildInstr(AMDGPU::V_READFIRSTLANE_B32) in constrainOpWithReadfirstlane()
1120 constrainGenericRegister(Reg, AMDGPU::VGPR_32RegClass, MRI); in constrainOpWithReadfirstlane()
1164 if (PtrBank == &AMDGPU::SGPRRegBank) { in applyMappingLoad()
1175 ApplyRegBankMapping O(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingLoad()
1220 ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingLoad()
1233 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingLoad()
1257 if (SizeBank != &AMDGPU::SGPRRegBank) in applyMappingDynStackAlloc()
1265 ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingDynStackAlloc()
1336 if (AMDGPU::splitMUBUFOffset(*Imm, SOffset, ImmOffset, &RBI.Subtarget, in setBufferOffsets()
1342 B.getMRI()->setRegBank(VOffsetReg, AMDGPU::VGPRRegBank); in setBufferOffsets()
1343 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets()
1352 AMDGPU::getBaseWithConstantOffset(*MRI, CombinedOffset); in setBufferOffsets()
1355 if (Offset > 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
1357 if (RBI.getRegBank(Base, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
1360 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets()
1368 B.getMRI()->setRegBank(VOffsetReg, AMDGPU::VGPRRegBank); in setBufferOffsets()
1376 if (MachineInstr *Add = getOpcodeDef(AMDGPU::G_ADD, CombinedOffset, *MRI)) { in setBufferOffsets()
1383 if (Src0Bank == &AMDGPU::VGPRRegBank && Src1Bank == &AMDGPU::SGPRRegBank) { in setBufferOffsets()
1389 if (Src0Bank == &AMDGPU::SGPRRegBank && Src1Bank == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
1398 if (RBI.getRegBank(CombinedOffset, *MRI, *RBI.TRI) == &AMDGPU::VGPRRegBank) { in setBufferOffsets()
1402 B.getMRI()->setRegBank(VOffsetReg, AMDGPU::VGPRRegBank); in setBufferOffsets()
1406 B.getMRI()->setRegBank(SOffsetReg, AMDGPU::SGPRRegBank); in setBufferOffsets()
1423 if (RSrcBank == &AMDGPU::SGPRRegBank && in applyMappingSBufferLoad()
1424 OffsetBank == &AMDGPU::SGPRRegBank) in applyMappingSBufferLoad()
1468 B.getMRI()->setRegBank(VIndex, AMDGPU::VGPRRegBank); in applyMappingSBufferLoad()
1480 MRI.setRegBank(LoadParts[i], AMDGPU::VGPRRegBank); in applyMappingSBufferLoad()
1487 B.buildInstr(AMDGPU::G_AMDGPU_BUFFER_LOAD) in applyMappingSBufferLoad()
1502 if (RSrcBank != &AMDGPU::SGPRRegBank) { in applyMappingSBufferLoad()
1523 if (RSrcBank == &AMDGPU::SGPRRegBank) in applyMappingSBufferLoad()
1544 if (DstBank == &AMDGPU::VGPRRegBank) { in applyMappingBFEIntrinsic()
1558 ApplyRegBankMapping ApplyBank(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingBFEIntrinsic()
1577 unsigned Opc = Ty == S32 ? (Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32) : in applyMappingBFEIntrinsic()
1578 (Signed ? AMDGPU::S_BFE_I64 : AMDGPU::S_BFE_U64); in applyMappingBFEIntrinsic()
1660 B.getMRI()->setRegBank(CmpReg, AMDGPU::SGPRRegBank); in lowerScalarMinMax()
1810 unsigned Opc = AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact; in selectStoreIntrinsic()
1813 Opc = Offen ? AMDGPU::BUFFER_STORE_BYTE_OFFEN_exact : in selectStoreIntrinsic()
1814 AMDGPU::BUFFER_STORE_BYTE_OFFSET_exact; in selectStoreIntrinsic()
1817 Opc = Offen ? AMDGPU::BUFFER_STORE_SHORT_OFFEN_exact : in selectStoreIntrinsic()
1818 AMDGPU::BUFFER_STORE_SHORT_OFFSET_exact; in selectStoreIntrinsic()
1821 Opc = Offen ? AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact : in selectStoreIntrinsic()
1822 AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact; in selectStoreIntrinsic()
1824 Opc = AMDGPU::getMUBUFOpcode(Opc, Size / 32); in selectStoreIntrinsic()
1862 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1865 return constrainGenericRegister(DstReg, AMDGPU::VGPR_32RegClass, MRI) && in buildVCopy()
1866 constrainGenericRegister(SrcReg, AMDGPU::SReg_32RegClass, MRI); in buildVCopy()
1869 Register TmpReg0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in buildVCopy()
1870 Register TmpReg1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in buildVCopy()
1872 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1874 .addUse(SrcReg, 0, AMDGPU::sub0); in buildVCopy()
1875 B.buildInstr(AMDGPU::V_MOV_B32_e32) in buildVCopy()
1877 .addUse(SrcReg, 0, AMDGPU::sub1); in buildVCopy()
1878 B.buildInstr(AMDGPU::REG_SEQUENCE) in buildVCopy()
1881 .addImm(AMDGPU::sub0) in buildVCopy()
1883 .addImm(AMDGPU::sub1); in buildVCopy()
1885 return constrainGenericRegister(SrcReg, AMDGPU::SReg_64RegClass, MRI) && in buildVCopy()
1886 constrainGenericRegister(DstReg, AMDGPU::VReg_64RegClass, MRI); in buildVCopy()
1903 MRI.setRegBank(MaterializedOffset.getReg(0), AMDGPU::SGPRRegBank); in reinsertVectorIndexAdd()
1904 MRI.setRegBank(Add.getReg(0), AMDGPU::SGPRRegBank); in reinsertVectorIndexAdd()
1917 if (ExtOpc == AMDGPU::G_ZEXT) { in extendLow32IntoHigh32()
1919 } else if (ExtOpc == AMDGPU::G_SEXT) { in extendLow32IntoHigh32()
1931 assert(ExtOpc == AMDGPU::G_ANYEXT && "not an integer extension"); in extendLow32IntoHigh32()
1946 bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank; in foldExtractEltToCmpSelect()
1965 (DstBank == AMDGPU::SGPRRegBank && in foldExtractEltToCmpSelect()
1966 SrcBank == AMDGPU::SGPRRegBank && in foldExtractEltToCmpSelect()
1967 IdxBank == AMDGPU::SGPRRegBank) ? AMDGPU::SGPRRegBank in foldExtractEltToCmpSelect()
1968 : AMDGPU::VCCRegBank; in foldExtractEltToCmpSelect()
1969 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1); in foldExtractEltToCmpSelect()
1971 if (CCBank == AMDGPU::VCCRegBank && IdxBank == AMDGPU::SGPRRegBank) { in foldExtractEltToCmpSelect()
1973 MRI.setRegBank(Idx, AMDGPU::VGPRRegBank); in foldExtractEltToCmpSelect()
1991 MRI.setRegBank(IC->getOperand(0).getReg(), AMDGPU::SGPRRegBank); in foldExtractEltToCmpSelect()
2028 bool IsDivergentIdx = IdxBank != AMDGPU::SGPRRegBank; in foldInsertEltToCmpSelect()
2049 (DstBank == AMDGPU::SGPRRegBank && in foldInsertEltToCmpSelect()
2050 SrcBank == AMDGPU::SGPRRegBank && in foldInsertEltToCmpSelect()
2051 InsBank == AMDGPU::SGPRRegBank && in foldInsertEltToCmpSelect()
2052 IdxBank == AMDGPU::SGPRRegBank) ? AMDGPU::SGPRRegBank in foldInsertEltToCmpSelect()
2053 : AMDGPU::VCCRegBank; in foldInsertEltToCmpSelect()
2054 LLT CCTy = (CCBank == AMDGPU::SGPRRegBank) ? S32 : LLT::scalar(1); in foldInsertEltToCmpSelect()
2056 if (CCBank == AMDGPU::VCCRegBank && IdxBank == AMDGPU::SGPRRegBank) { in foldInsertEltToCmpSelect()
2058 MRI.setRegBank(Idx, AMDGPU::VGPRRegBank); in foldInsertEltToCmpSelect()
2076 MRI.setRegBank(IC->getOperand(0).getReg(), AMDGPU::SGPRRegBank); in foldInsertEltToCmpSelect()
2112 case AMDGPU::G_PHI: { in applyMappingImpl()
2121 if (DstBank == &AMDGPU::VCCRegBank) { in applyMappingImpl()
2134 if (SrcBank != &AMDGPU::VCCRegBank) { in applyMappingImpl()
2139 MRI.setRegBank(Copy.getReg(0), AMDGPU::VCCRegBank); in applyMappingImpl()
2162 case AMDGPU::G_ICMP: in applyMappingImpl()
2163 case AMDGPU::G_UADDO: in applyMappingImpl()
2164 case AMDGPU::G_USUBO: in applyMappingImpl()
2165 case AMDGPU::G_UADDE: in applyMappingImpl()
2166 case AMDGPU::G_SADDE: in applyMappingImpl()
2167 case AMDGPU::G_USUBE: in applyMappingImpl()
2168 case AMDGPU::G_SSUBE: { in applyMappingImpl()
2169 unsigned BoolDstOp = Opc == AMDGPU::G_ICMP ? 0 : 1; in applyMappingImpl()
2174 if (DstBank != &AMDGPU::SGPRRegBank) in applyMappingImpl()
2183 MRI.setRegBank(NewDstReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2189 MRI.setRegBank(NewSrcReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2205 case AMDGPU::G_SELECT: { in applyMappingImpl()
2217 if (CondBank == &AMDGPU::SGPRRegBank) { in applyMappingImpl()
2221 MRI.setRegBank(NewCondReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2259 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingImpl()
2263 case AMDGPU::G_BRCOND: { in applyMappingImpl()
2269 if (CondBank == &AMDGPU::SGPRRegBank) { in applyMappingImpl()
2273 MRI.setRegBank(NewCondReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2282 case AMDGPU::G_AND: in applyMappingImpl()
2283 case AMDGPU::G_OR: in applyMappingImpl()
2284 case AMDGPU::G_XOR: { in applyMappingImpl()
2293 if (DstBank == &AMDGPU::VCCRegBank) in applyMappingImpl()
2346 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingImpl()
2350 case AMDGPU::G_ADD: in applyMappingImpl()
2351 case AMDGPU::G_SUB: in applyMappingImpl()
2352 case AMDGPU::G_MUL: in applyMappingImpl()
2353 case AMDGPU::G_SHL: in applyMappingImpl()
2354 case AMDGPU::G_LSHR: in applyMappingImpl()
2355 case AMDGPU::G_ASHR: { in applyMappingImpl()
2366 if (DstBank == &AMDGPU::VGPRRegBank) in applyMappingImpl()
2373 ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingImpl()
2383 = unpackV2S16ToS32(B, MI.getOperand(1).getReg(), AMDGPU::G_ANYEXT); in applyMappingImpl()
2385 = unpackV2S16ToS32(B, MI.getOperand(2).getReg(), AMDGPU::G_ANYEXT); in applyMappingImpl()
2397 if (Opc == AMDGPU::G_SHL || Opc == AMDGPU::G_LSHR || in applyMappingImpl()
2398 Opc == AMDGPU::G_ASHR) { in applyMappingImpl()
2407 case AMDGPU::G_SMIN: in applyMappingImpl()
2408 case AMDGPU::G_SMAX: in applyMappingImpl()
2409 case AMDGPU::G_UMIN: in applyMappingImpl()
2410 case AMDGPU::G_UMAX: { in applyMappingImpl()
2414 if (DstBank == &AMDGPU::VGPRRegBank) in applyMappingImpl()
2427 ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingImpl()
2460 ApplyRegBankMapping ApplySALU(*this, MRI, &AMDGPU::SGPRRegBank); in applyMappingImpl()
2475 case AMDGPU::G_SEXT_INREG: { in applyMappingImpl()
2482 ApplyRegBankMapping O(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingImpl()
2509 MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank); in applyMappingImpl()
2513 case AMDGPU::G_CTPOP: in applyMappingImpl()
2514 case AMDGPU::G_CTLZ_ZERO_UNDEF: in applyMappingImpl()
2515 case AMDGPU::G_CTTZ_ZERO_UNDEF: { in applyMappingImpl()
2521 if (DstBank == &AMDGPU::SGPRRegBank) in applyMappingImpl()
2530 ApplyRegBankMapping ApplyVALU(*this, MRI, &AMDGPU::VGPRRegBank); in applyMappingImpl()
2538 case AMDGPU::G_SEXT: in applyMappingImpl()
2539 case AMDGPU::G_ZEXT: in applyMappingImpl()
2540 case AMDGPU::G_ANYEXT: { in applyMappingImpl()
2543 const bool Signed = Opc == AMDGPU::G_SEXT; in applyMappingImpl()
2554 SrcBank != &AMDGPU::SGPRRegBank && in applyMappingImpl()
2555 SrcBank != &AMDGPU::VCCRegBank && in applyMappingImpl()
2566 } else if (Opc == AMDGPU::G_ZEXT) { in applyMappingImpl()
2584 if (SrcBank == &AMDGPU::VCCRegBank) { in applyMappingImpl()
2587 const RegisterBank *DstBank = &AMDGPU::VGPRRegBank; in applyMappingImpl()
2592 SrcBank->getID() == AMDGPU::SGPRRegBankID; in applyMappingImpl()
2620 case AMDGPU::G_BUILD_VECTOR: in applyMappingImpl()
2621 case AMDGPU::G_BUILD_VECTOR_TRUNC: { in applyMappingImpl()
2633 if (DstBank == &AMDGPU::SGPRRegBank) in applyMappingImpl()
2650 if (Opc == AMDGPU::G_BUILD_VECTOR) { in applyMappingImpl()
2683 case AMDGPU::G_EXTRACT_VECTOR_ELT: { in applyMappingImpl()
2711 AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(2).getReg()); in applyMappingImpl()
2717 bool ShouldMoveIndexIntoLoop = IdxBank != &AMDGPU::SGPRRegBank && in applyMappingImpl()
2729 const bool NeedCopyToVGPR = DstBank == &AMDGPU::VGPRRegBank && in applyMappingImpl()
2730 SrcBank == &AMDGPU::SGPRRegBank; in applyMappingImpl()
2739 MRI.setRegBank(TmpReg, AMDGPU::SGPRRegBank); in applyMappingImpl()
2778 MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2779 MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2780 MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2799 MRI.setRegBank(TmpReg0, AMDGPU::SGPRRegBank); in applyMappingImpl()
2800 MRI.setRegBank(TmpReg1, AMDGPU::SGPRRegBank); in applyMappingImpl()
2816 case AMDGPU::G_INSERT_VECTOR_ELT: { in applyMappingImpl()
2842 AMDGPU::getBaseWithConstantOffset(MRI, MI.getOperand(3).getReg()); in applyMappingImpl()
2848 bool ShouldMoveIndexIntoLoop = IdxBank != &AMDGPU::SGPRRegBank && in applyMappingImpl()
2903 MRI.setRegBank(One.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2904 MRI.setRegBank(IdxLo.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2905 MRI.setRegBank(IdxHi.getReg(0), AMDGPU::SGPRRegBank); in applyMappingImpl()
2936 case AMDGPU::G_AMDGPU_BUFFER_LOAD: in applyMappingImpl()
2937 case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: in applyMappingImpl()
2938 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT: in applyMappingImpl()
2939 case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE: in applyMappingImpl()
2940 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE: in applyMappingImpl()
2941 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT: in applyMappingImpl()
2942 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16: in applyMappingImpl()
2943 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT: in applyMappingImpl()
2944 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16: in applyMappingImpl()
2945 case AMDGPU::G_AMDGPU_BUFFER_STORE: in applyMappingImpl()
2946 case AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE: in applyMappingImpl()
2947 case AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT: in applyMappingImpl()
2948 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT: in applyMappingImpl()
2949 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16: in applyMappingImpl()
2950 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT: in applyMappingImpl()
2951 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16: { in applyMappingImpl()
2956 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP: in applyMappingImpl()
2957 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD: in applyMappingImpl()
2958 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB: in applyMappingImpl()
2959 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN: in applyMappingImpl()
2960 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN: in applyMappingImpl()
2961 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX: in applyMappingImpl()
2962 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX: in applyMappingImpl()
2963 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND: in applyMappingImpl()
2964 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR: in applyMappingImpl()
2965 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR: in applyMappingImpl()
2966 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC: in applyMappingImpl()
2967 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: { in applyMappingImpl()
2972 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD: { in applyMappingImpl()
2977 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP: { in applyMappingImpl()
2982 case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: { in applyMappingImpl()
2986 case AMDGPU::G_INTRINSIC: { in applyMappingImpl()
3042 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD: in applyMappingImpl()
3043 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: { in applyMappingImpl()
3044 const AMDGPU::RsrcIntrinsic *RSrcIntrin in applyMappingImpl()
3045 = AMDGPU::lookupRsrcIntrinsic(MI.getIntrinsicID()); in applyMappingImpl()
3053 case AMDGPU::G_AMDGPU_INTRIN_BVH_INTERSECT_RAY: { in applyMappingImpl()
3058 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: { in applyMappingImpl()
3100 if (const AMDGPU::RsrcIntrinsic *RSrcIntrin = in applyMappingImpl()
3101 AMDGPU::lookupRsrcIntrinsic(IntrID)) { in applyMappingImpl()
3116 case AMDGPU::G_LOAD: in applyMappingImpl()
3117 case AMDGPU::G_ZEXTLOAD: in applyMappingImpl()
3118 case AMDGPU::G_SEXTLOAD: { in applyMappingImpl()
3123 case AMDGPU::G_DYN_STACKALLOC: in applyMappingImpl()
3138 if (RB0 == AMDGPU::InvalidRegBankID) in regBankUnion()
3140 if (RB1 == AMDGPU::InvalidRegBankID) in regBankUnion()
3143 if (RB0 == AMDGPU::SGPRRegBankID && RB1 == AMDGPU::SGPRRegBankID) in regBankUnion()
3144 return AMDGPU::SGPRRegBankID; in regBankUnion()
3146 if (RB0 == AMDGPU::AGPRRegBankID && RB1 == AMDGPU::AGPRRegBankID) in regBankUnion()
3147 return AMDGPU::AGPRRegBankID; in regBankUnion()
3149 return AMDGPU::VGPRRegBankID; in regBankUnion()
3153 if (RB0 == AMDGPU::InvalidRegBankID) in regBankBoolUnion()
3155 if (RB1 == AMDGPU::InvalidRegBankID) in regBankBoolUnion()
3161 if (RB0 == AMDGPU::VCCRegBankID || RB1 == AMDGPU::VCCRegBankID) in regBankBoolUnion()
3162 return AMDGPU::VCCRegBankID; in regBankBoolUnion()
3170 unsigned RegBank = AMDGPU::InvalidRegBankID; in getMappingType()
3178 if (RegBank == AMDGPU::VGPRRegBankID) in getMappingType()
3194 if (Bank->getID() != AMDGPU::SGPRRegBankID) in isSALUMapping()
3213 OpdsMapping[i] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getDefaultMappingSOP()
3235 unsigned BankID = Size == 1 ? AMDGPU::VCCRegBankID : AMDGPU::VGPRRegBankID; in getDefaultMappingVOP()
3236 OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size); in getDefaultMappingVOP()
3255 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getDefaultMappingAllVGPR()
3294 unsigned NewBank = getRegBankID(OpReg, MRI, AMDGPU::SGPRRegBankID); in getImageMapping()
3295 OpdsMapping[I] = AMDGPU::getValueMapping(NewBank, Size); in getImageMapping()
3298 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getImageMapping()
3312 !AMDGPU::isFlatGlobalAddrSpace(PtrTy.getAddressSpace())) in getValueMappingForPtr()
3313 return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getValueMappingForPtr()
3318 return AMDGPU::getValueMapping(PtrBank->getID(), Size); in getValueMappingForPtr()
3338 if (PtrBank == &AMDGPU::SGPRRegBank && AMDGPU::isFlatGlobalAddrSpace(AS)) { in getInstrMappingForLoad()
3341 ValMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMappingForLoad()
3342 PtrMapping = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, PtrSize); in getInstrMappingForLoad()
3344 ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMappingForLoad()
3349 AMDGPU::VGPRRegBankID : AMDGPU::SGPRRegBankID; in getInstrMappingForLoad()
3351 PtrMapping = AMDGPU::getValueMapping(PtrBankID, PtrSize); in getInstrMappingForLoad()
3354 ValMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMappingForLoad()
3355 PtrMapping = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, PtrSize); in getInstrMappingForLoad()
3382 unsigned Bank = getRegBankID(Reg, MRI, AMDGPU::SGPRRegBankID); in getSGPROpMapping()
3384 return AMDGPU::getValueMapping(Bank, Size); in getSGPROpMapping()
3392 return AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getVGPROpMapping()
3400 return AMDGPU::getValueMapping(AMDGPU::AGPRRegBankID, Size); in getAGPROpMapping()
3417 if (MI.isCopy() || MI.getOpcode() == AMDGPU::G_FREEZE) { in getInstrMapping()
3436 if (MI.getOpcode() == AMDGPU::G_FREEZE) in getInstrMapping()
3447 unsigned BankID = AMDGPU::SGPRRegBankID; in getInstrMapping()
3453 if (OpBank != AMDGPU::SGPRRegBankID) { in getInstrMapping()
3454 BankID = AMDGPU::VGPRRegBankID; in getInstrMapping()
3471 unsigned ResultBank = AMDGPU::InvalidRegBankID; in getInstrMapping()
3483 if (!Bank || Bank->getID() == AMDGPU::VGPRRegBankID) { in getInstrMapping()
3484 ResultBank = AMDGPU::VGPRRegBankID; in getInstrMapping()
3493 assert(ResultBank != AMDGPU::InvalidRegBankID); in getInstrMapping()
3514 case AMDGPU::G_AND: in getInstrMapping()
3515 case AMDGPU::G_OR: in getInstrMapping()
3516 case AMDGPU::G_XOR: { in getInstrMapping()
3522 unsigned TargetBankID = AMDGPU::InvalidRegBankID; in getInstrMapping()
3523 unsigned BankLHS = AMDGPU::InvalidRegBankID; in getInstrMapping()
3524 unsigned BankRHS = AMDGPU::InvalidRegBankID; in getInstrMapping()
3527 if (DstBank == &AMDGPU::VCCRegBank) { in getInstrMapping()
3528 TargetBankID = AMDGPU::VCCRegBankID; in getInstrMapping()
3529 BankLHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3530 BankRHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3533 AMDGPU::SGPRRegBankID); in getInstrMapping()
3535 AMDGPU::SGPRRegBankID); in getInstrMapping()
3539 AMDGPU::VCCRegBankID); in getInstrMapping()
3541 AMDGPU::VCCRegBankID); in getInstrMapping()
3544 if (BankLHS == AMDGPU::VGPRRegBankID || BankRHS == AMDGPU::VGPRRegBankID) { in getInstrMapping()
3545 TargetBankID = AMDGPU::VGPRRegBankID; in getInstrMapping()
3546 } else if (BankLHS == AMDGPU::VCCRegBankID || BankRHS == AMDGPU::VCCRegBankID) { in getInstrMapping()
3547 TargetBankID = AMDGPU::VCCRegBankID; in getInstrMapping()
3548 BankLHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3549 BankRHS = AMDGPU::VCCRegBankID; in getInstrMapping()
3550 } else if (BankLHS == AMDGPU::SGPRRegBankID && BankRHS == AMDGPU::SGPRRegBankID) { in getInstrMapping()
3551 TargetBankID = AMDGPU::SGPRRegBankID; in getInstrMapping()
3555 OpdsMapping[0] = AMDGPU::getValueMapping(TargetBankID, Size); in getInstrMapping()
3556 OpdsMapping[1] = AMDGPU::getValueMapping(BankLHS, Size); in getInstrMapping()
3557 OpdsMapping[2] = AMDGPU::getValueMapping(BankRHS, Size); in getInstrMapping()
3564 OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
3567 OpdsMapping[0] = getValueMappingSGPR64Only(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3569 OpdsMapping[1] = AMDGPU::getValueMapping(Bank1, Size); in getInstrMapping()
3572 OpdsMapping[2] = AMDGPU::getValueMapping(Bank2, Size); in getInstrMapping()
3580 case AMDGPU::G_PTR_ADD: in getInstrMapping()
3581 case AMDGPU::G_PTRMASK: in getInstrMapping()
3582 case AMDGPU::G_ADD: in getInstrMapping()
3583 case AMDGPU::G_SUB: in getInstrMapping()
3584 case AMDGPU::G_MUL: in getInstrMapping()
3585 case AMDGPU::G_SHL: in getInstrMapping()
3586 case AMDGPU::G_LSHR: in getInstrMapping()
3587 case AMDGPU::G_ASHR: in getInstrMapping()
3588 case AMDGPU::G_UADDO: in getInstrMapping()
3589 case AMDGPU::G_USUBO: in getInstrMapping()
3590 case AMDGPU::G_UADDE: in getInstrMapping()
3591 case AMDGPU::G_SADDE: in getInstrMapping()
3592 case AMDGPU::G_USUBE: in getInstrMapping()
3593 case AMDGPU::G_SSUBE: in getInstrMapping()
3594 case AMDGPU::G_SMIN: in getInstrMapping()
3595 case AMDGPU::G_SMAX: in getInstrMapping()
3596 case AMDGPU::G_UMIN: in getInstrMapping()
3597 case AMDGPU::G_UMAX: in getInstrMapping()
3598 case AMDGPU::G_SHUFFLE_VECTOR: in getInstrMapping()
3603 case AMDGPU::G_SADDSAT: // FIXME: Could lower sat ops for SALU in getInstrMapping()
3604 case AMDGPU::G_SSUBSAT: in getInstrMapping()
3605 case AMDGPU::G_UADDSAT: in getInstrMapping()
3606 case AMDGPU::G_USUBSAT: in getInstrMapping()
3607 case AMDGPU::G_FADD: in getInstrMapping()
3608 case AMDGPU::G_FSUB: in getInstrMapping()
3609 case AMDGPU::G_FPTOSI: in getInstrMapping()
3610 case AMDGPU::G_FPTOUI: in getInstrMapping()
3611 case AMDGPU::G_FMUL: in getInstrMapping()
3612 case AMDGPU::G_FMA: in getInstrMapping()
3613 case AMDGPU::G_FMAD: in getInstrMapping()
3614 case AMDGPU::G_FSQRT: in getInstrMapping()
3615 case AMDGPU::G_FFLOOR: in getInstrMapping()
3616 case AMDGPU::G_FCEIL: in getInstrMapping()
3617 case AMDGPU::G_FRINT: in getInstrMapping()
3618 case AMDGPU::G_SITOFP: in getInstrMapping()
3619 case AMDGPU::G_UITOFP: in getInstrMapping()
3620 case AMDGPU::G_FPTRUNC: in getInstrMapping()
3621 case AMDGPU::G_FPEXT: in getInstrMapping()
3622 case AMDGPU::G_FEXP2: in getInstrMapping()
3623 case AMDGPU::G_FLOG2: in getInstrMapping()
3624 case AMDGPU::G_FMINNUM: in getInstrMapping()
3625 case AMDGPU::G_FMAXNUM: in getInstrMapping()
3626 case AMDGPU::G_FMINNUM_IEEE: in getInstrMapping()
3627 case AMDGPU::G_FMAXNUM_IEEE: in getInstrMapping()
3628 case AMDGPU::G_FCANONICALIZE: in getInstrMapping()
3629 case AMDGPU::G_INTRINSIC_TRUNC: in getInstrMapping()
3630 case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar? in getInstrMapping()
3631 case AMDGPU::G_FSHR: // TODO: Expand for scalar in getInstrMapping()
3632 case AMDGPU::G_AMDGPU_FFBH_U32: in getInstrMapping()
3633 case AMDGPU::G_AMDGPU_FMIN_LEGACY: in getInstrMapping()
3634 case AMDGPU::G_AMDGPU_FMAX_LEGACY: in getInstrMapping()
3635 case AMDGPU::G_AMDGPU_RCP_IFLAG: in getInstrMapping()
3636 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0: in getInstrMapping()
3637 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1: in getInstrMapping()
3638 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2: in getInstrMapping()
3639 case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3: in getInstrMapping()
3641 case AMDGPU::G_UMULH: in getInstrMapping()
3642 case AMDGPU::G_SMULH: { in getInstrMapping()
3647 case AMDGPU::G_IMPLICIT_DEF: { in getInstrMapping()
3649 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
3652 case AMDGPU::G_FCONSTANT: in getInstrMapping()
3653 case AMDGPU::G_CONSTANT: in getInstrMapping()
3654 case AMDGPU::G_GLOBAL_VALUE: in getInstrMapping()
3655 case AMDGPU::G_BLOCK_ADDR: in getInstrMapping()
3656 case AMDGPU::G_READCYCLECOUNTER: { in getInstrMapping()
3658 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
3661 case AMDGPU::G_FRAME_INDEX: { in getInstrMapping()
3665 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3668 case AMDGPU::G_DYN_STACKALLOC: { in getInstrMapping()
3670 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, 32); in getInstrMapping()
3672 OpdsMapping[1] = AMDGPU::getValueMapping(SrcBankID, 32); in getInstrMapping()
3675 case AMDGPU::G_INSERT: { in getInstrMapping()
3680 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize); in getInstrMapping()
3681 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize); in getInstrMapping()
3682 OpdsMapping[2] = AMDGPU::getValueMapping(BankID, EltSize); in getInstrMapping()
3686 case AMDGPU::G_EXTRACT: { in getInstrMapping()
3690 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize); in getInstrMapping()
3691 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize); in getInstrMapping()
3695 case AMDGPU::G_BUILD_VECTOR: in getInstrMapping()
3696 case AMDGPU::G_BUILD_VECTOR_TRUNC: { in getInstrMapping()
3705 OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize); in getInstrMapping()
3706 OpdsMapping[1] = AMDGPU::getValueMapping(Src0BankID, SrcSize); in getInstrMapping()
3707 OpdsMapping[2] = AMDGPU::getValueMapping(Src1BankID, SrcSize); in getInstrMapping()
3713 case AMDGPU::G_MERGE_VALUES: in getInstrMapping()
3714 case AMDGPU::G_CONCAT_VECTORS: { in getInstrMapping()
3719 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); in getInstrMapping()
3722 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize); in getInstrMapping()
3725 case AMDGPU::G_BITCAST: in getInstrMapping()
3726 case AMDGPU::G_INTTOPTR: in getInstrMapping()
3727 case AMDGPU::G_PTRTOINT: in getInstrMapping()
3728 case AMDGPU::G_BITREVERSE: in getInstrMapping()
3729 case AMDGPU::G_FABS: in getInstrMapping()
3730 case AMDGPU::G_FNEG: { in getInstrMapping()
3733 OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); in getInstrMapping()
3736 case AMDGPU::G_CTLZ_ZERO_UNDEF: in getInstrMapping()
3737 case AMDGPU::G_CTTZ_ZERO_UNDEF: in getInstrMapping()
3738 case AMDGPU::G_CTPOP: { in getInstrMapping()
3741 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, 32); in getInstrMapping()
3746 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size); in getInstrMapping()
3749 case AMDGPU::G_TRUNC: { in getInstrMapping()
3755 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize); in getInstrMapping()
3756 OpdsMapping[1] = AMDGPU::getValueMapping(Bank, SrcSize); in getInstrMapping()
3759 case AMDGPU::G_ZEXT: in getInstrMapping()
3760 case AMDGPU::G_SEXT: in getInstrMapping()
3761 case AMDGPU::G_ANYEXT: in getInstrMapping()
3762 case AMDGPU::G_SEXT_INREG: { in getInstrMapping()
3772 case AMDGPU::SGPRRegBankID: in getInstrMapping()
3773 DstBank = AMDGPU::SGPRRegBankID; in getInstrMapping()
3776 DstBank = AMDGPU::VGPRRegBankID; in getInstrMapping()
3782 OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(DstBank, DstSize); in getInstrMapping()
3783 OpdsMapping[1] = AMDGPU::getValueMappingSGPR64Only(SrcBank->getID(), in getInstrMapping()
3787 case AMDGPU::G_FCMP: { in getInstrMapping()
3790 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
3792 OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size); in getInstrMapping()
3793 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3796 case AMDGPU::G_STORE: { in getInstrMapping()
3803 AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
3808 case AMDGPU::G_ICMP: { in getInstrMapping()
3815 AMDGPU::SGPRRegBankID); in getInstrMapping()
3819 bool CanUseSCC = DstBank == AMDGPU::SGPRRegBankID && in getInstrMapping()
3820 Op2Bank == AMDGPU::SGPRRegBankID && in getInstrMapping()
3821 Op3Bank == AMDGPU::SGPRRegBankID && in getInstrMapping()
3826 DstBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; in getInstrMapping()
3827 unsigned SrcBank = CanUseSCC ? AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
3833 OpdsMapping[0] = AMDGPU::getValueMapping(DstBank, ResultSize); in getInstrMapping()
3834 OpdsMapping[2] = AMDGPU::getValueMapping(SrcBank, Size); in getInstrMapping()
3835 OpdsMapping[3] = AMDGPU::getValueMapping(SrcBank, Size); in getInstrMapping()
3838 case AMDGPU::G_EXTRACT_VECTOR_ELT: { in getInstrMapping()
3847 OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(OutputBankID, DstSize); in getInstrMapping()
3848 OpdsMapping[1] = AMDGPU::getValueMapping(SrcBankID, SrcSize); in getInstrMapping()
3851 OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, IdxSize); in getInstrMapping()
3854 case AMDGPU::G_INSERT_VECTOR_ELT: { in getInstrMapping()
3856 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
3864 OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
3865 OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, VecSize); in getInstrMapping()
3869 if (InsertSize == 64 && OutputBankID == AMDGPU::VGPRRegBankID) { in getInstrMapping()
3870 OpdsMapping[2] = AMDGPU::getValueMappingSplit64(InsertEltBankID, in getInstrMapping()
3874 OpdsMapping[2] = AMDGPU::getValueMapping(InsertEltBankID, InsertSize); in getInstrMapping()
3878 OpdsMapping[3] = AMDGPU::getValueMapping(IdxBankID, IdxSize); in getInstrMapping()
3881 case AMDGPU::G_UNMERGE_VALUES: { in getInstrMapping()
3888 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
3892 case AMDGPU::G_AMDGPU_BUFFER_LOAD: in getInstrMapping()
3893 case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE: in getInstrMapping()
3894 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE: in getInstrMapping()
3895 case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT: in getInstrMapping()
3896 case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT: in getInstrMapping()
3897 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT: in getInstrMapping()
3898 case AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16: in getInstrMapping()
3899 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT: in getInstrMapping()
3900 case AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16: in getInstrMapping()
3901 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT: in getInstrMapping()
3902 case AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16: in getInstrMapping()
3903 case AMDGPU::G_AMDGPU_BUFFER_STORE: in getInstrMapping()
3904 case AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE: in getInstrMapping()
3905 case AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT: in getInstrMapping()
3906 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT: in getInstrMapping()
3907 case AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16: { in getInstrMapping()
3926 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP: in getInstrMapping()
3927 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD: in getInstrMapping()
3928 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB: in getInstrMapping()
3929 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN: in getInstrMapping()
3930 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN: in getInstrMapping()
3931 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX: in getInstrMapping()
3932 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX: in getInstrMapping()
3933 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND: in getInstrMapping()
3934 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR: in getInstrMapping()
3935 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR: in getInstrMapping()
3936 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC: in getInstrMapping()
3937 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC: in getInstrMapping()
3938 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD: { in getInstrMapping()
3961 case AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP: { in getInstrMapping()
3987 case AMDGPU::G_AMDGPU_S_BUFFER_LOAD: { in getInstrMapping()
4000 OpdsMapping[0] = AMDGPU::getValueMapping(ResultBank, Size0); in getInstrMapping()
4003 case AMDGPU::G_INTRINSIC: { in getInstrMapping()
4082 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4088 = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size); in getInstrMapping()
4092 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4098 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Dst0Size); in getInstrMapping()
4099 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Dst1Size); in getInstrMapping()
4102 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4103 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4112 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, DstSize); in getInstrMapping()
4113 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Src0Size); in getInstrMapping()
4114 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Src1Size); in getInstrMapping()
4121 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize); in getInstrMapping()
4123 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
4124 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, OpSize); in getInstrMapping()
4131 unsigned IdxBank = getRegBankID(IdxReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4132 OpdsMapping[3] = AMDGPU::getValueMapping(IdxBank, IdxSize); in getInstrMapping()
4138 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize); in getInstrMapping()
4139 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4146 unsigned SrcBank = getRegBankID(SrcReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4149 unsigned IdxBank = getRegBankID(IdxReg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4150 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4154 OpdsMapping[2] = AMDGPU::getValueMapping(SrcBank, SrcSize); in getInstrMapping()
4155 OpdsMapping[3] = AMDGPU::getValueMapping(IdxBank, IdxSize); in getInstrMapping()
4156 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, SrcSize); in getInstrMapping()
4161 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4162 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4163 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4169 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4170 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4171 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size); in getInstrMapping()
4215 unsigned M0Bank = getRegBankID(M0Reg, MRI, AMDGPU::SGPRRegBankID); in getInstrMapping()
4218 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4220 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4224 OpdsMapping[M0Idx] = AMDGPU::getValueMapping(M0Bank, 32); in getInstrMapping()
4230 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, DstSize); in getInstrMapping()
4231 OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, SrcSize); in getInstrMapping()
4237 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_LOAD: in getInstrMapping()
4238 case AMDGPU::G_AMDGPU_INTRIN_IMAGE_STORE: { in getInstrMapping()
4240 const AMDGPU::RsrcIntrinsic *RSrcIntrin = AMDGPU::lookupRsrcIntrinsic(IntrID); in getInstrMapping()
4248 case AMDGPU::G_AMDGPU_INTRIN_BVH_INTERSECT_RAY: { in getInstrMapping()
4250 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 128); in getInstrMapping()
4253 OpdsMapping[I] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4256 case AMDGPU::G_INTRINSIC_W_SIDE_EFFECTS: { in getInstrMapping()
4264 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4273 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4275 AMDGPU::SGPRRegBankID); in getInstrMapping()
4276 OpdsMapping[2] = AMDGPU::getValueMapping(M0Bank, 32); in getInstrMapping()
4277 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4283 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, DstSize); in getInstrMapping()
4288 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4289 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4293 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4294 OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4295 OpdsMapping[5] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4296 OpdsMapping[6] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4302 AMDGPU::SGPRRegBankID); in getInstrMapping()
4303 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4309 AMDGPU::SGPRRegBankID); in getInstrMapping()
4310 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4315 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4320 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4321 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); in getInstrMapping()
4322 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, WaveSize); in getInstrMapping()
4326 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, 1); in getInstrMapping()
4368 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size); in getInstrMapping()
4374 OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32); in getInstrMapping()
4378 AMDGPU::SGPRRegBankID); in getInstrMapping()
4379 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4387 AMDGPU::SGPRRegBankID); in getInstrMapping()
4388 OpdsMapping[1] = AMDGPU::getValueMapping(Bank, 32); in getInstrMapping()
4396 case AMDGPU::G_SELECT: { in getInstrMapping()
4399 AMDGPU::SGPRRegBankID); in getInstrMapping()
4401 AMDGPU::SGPRRegBankID); in getInstrMapping()
4402 bool SGPRSrcs = Op2Bank == AMDGPU::SGPRRegBankID && in getInstrMapping()
4403 Op3Bank == AMDGPU::SGPRRegBankID; in getInstrMapping()
4406 AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; in getInstrMapping()
4409 if (CondBank == AMDGPU::SGPRRegBankID) in getInstrMapping()
4410 CondBank = SGPRSrcs ? AMDGPU::SGPRRegBankID : AMDGPU::VCCRegBankID; in getInstrMapping()
4411 else if (CondBank == AMDGPU::VGPRRegBankID) in getInstrMapping()
4412 CondBank = AMDGPU::VCCRegBankID; in getInstrMapping()
4414 unsigned Bank = SGPRSrcs && CondBank == AMDGPU::SGPRRegBankID ? in getInstrMapping()
4415 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID; in getInstrMapping()
4417 assert(CondBank == AMDGPU::VCCRegBankID || CondBank == AMDGPU::SGPRRegBankID); in getInstrMapping()
4421 OpdsMapping[0] = AMDGPU::getValueMappingSGPR64Only(Bank, Size); in getInstrMapping()
4422 OpdsMapping[1] = AMDGPU::getValueMapping(CondBank, 1); in getInstrMapping()
4423 OpdsMapping[2] = AMDGPU::getValueMappingSGPR64Only(Bank, Size); in getInstrMapping()
4424 OpdsMapping[3] = AMDGPU::getValueMappingSGPR64Only(Bank, Size); in getInstrMapping()
4426 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4427 OpdsMapping[1] = AMDGPU::getValueMapping(CondBank, 1); in getInstrMapping()
4428 OpdsMapping[2] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4429 OpdsMapping[3] = AMDGPU::getValueMapping(Bank, Size); in getInstrMapping()
4435 case AMDGPU::G_LOAD: in getInstrMapping()
4436 case AMDGPU::G_ZEXTLOAD: in getInstrMapping()
4437 case AMDGPU::G_SEXTLOAD: in getInstrMapping()
4440 case AMDGPU::G_ATOMICRMW_XCHG: in getInstrMapping()
4441 case AMDGPU::G_ATOMICRMW_ADD: in getInstrMapping()
4442 case AMDGPU::G_ATOMICRMW_SUB: in getInstrMapping()
4443 case AMDGPU::G_ATOMICRMW_AND: in getInstrMapping()
4444 case AMDGPU::G_ATOMICRMW_OR: in getInstrMapping()
4445 case AMDGPU::G_ATOMICRMW_XOR: in getInstrMapping()
4446 case AMDGPU::G_ATOMICRMW_MAX: in getInstrMapping()
4447 case AMDGPU::G_ATOMICRMW_MIN: in getInstrMapping()
4448 case AMDGPU::G_ATOMICRMW_UMAX: in getInstrMapping()
4449 case AMDGPU::G_ATOMICRMW_UMIN: in getInstrMapping()
4450 case AMDGPU::G_ATOMICRMW_FADD: in getInstrMapping()
4451 case AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG: in getInstrMapping()
4452 case AMDGPU::G_AMDGPU_ATOMIC_INC: in getInstrMapping()
4453 case AMDGPU::G_AMDGPU_ATOMIC_DEC: in getInstrMapping()
4454 case AMDGPU::G_AMDGPU_ATOMIC_FMIN: in getInstrMapping()
4455 case AMDGPU::G_AMDGPU_ATOMIC_FMAX: { in getInstrMapping()
4461 case AMDGPU::G_ATOMIC_CMPXCHG: { in getInstrMapping()
4468 case AMDGPU::G_BRCOND: { in getInstrMapping()
4470 AMDGPU::SGPRRegBankID); in getInstrMapping()
4472 if (Bank != AMDGPU::SGPRRegBankID) in getInstrMapping()
4473 Bank = AMDGPU::VCCRegBankID; in getInstrMapping()
4475 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, 1); in getInstrMapping()