Lines Matching refs:addPass
691 addPass(createGVNPass()); in addEarlyCSEOrGVNPass()
693 addPass(createEarlyCSEPass()); in addEarlyCSEOrGVNPass()
697 addPass(createLICMPass()); in addStraightLineScalarOptimizationPasses()
698 addPass(createSeparateConstOffsetFromGEPPass()); in addStraightLineScalarOptimizationPasses()
699 addPass(createSpeculativeExecutionPass()); in addStraightLineScalarOptimizationPasses()
702 addPass(createStraightLineStrengthReducePass()); in addStraightLineScalarOptimizationPasses()
707 addPass(createNaryReassociatePass()); in addStraightLineScalarOptimizationPasses()
710 addPass(createEarlyCSEPass()); in addStraightLineScalarOptimizationPasses()
721 addPass(createAMDGPUPrintfRuntimeBinding()); in addIRPasses()
725 addPass(createAMDGPUFixFunctionBitcastsPass()); in addIRPasses()
728 addPass(createAMDGPUPropagateAttributesEarlyPass(&TM)); in addIRPasses()
730 addPass(createAtomicExpandPass()); in addIRPasses()
733 addPass(createAMDGPULowerIntrinsicsPass()); in addIRPasses()
736 addPass(createAMDGPUAlwaysInlinePass()); in addIRPasses()
737 addPass(createAlwaysInlinerLegacyPass()); in addIRPasses()
743 addPass(createBarrierNoopPass()); in addIRPasses()
747 addPass(createR600OpenCLImageTypeLoweringPass()); in addIRPasses()
750 addPass(createAMDGPUOpenCLEnqueuedBlockLoweringPass()); in addIRPasses()
753 addPass(createInferAddressSpacesPass()); in addIRPasses()
754 addPass(createAMDGPUPromoteAlloca()); in addIRPasses()
757 addPass(createSROAPass()); in addIRPasses()
763 addPass(createAMDGPUAAWrapperPass()); in addIRPasses()
764 addPass(createExternalAAWrapperPass([](Pass &P, Function &, in addIRPasses()
774 addPass(createAMDGPUCodeGenPreparePass()); in addIRPasses()
797 addPass(createAMDGPUAnnotateKernelFeaturesPass()); in addCodeGenPrepare()
801 addPass(createAMDGPULowerKernelArgumentsPass()); in addCodeGenPrepare()
803 addPass(&AMDGPUPerfHintAnalysisID); in addCodeGenPrepare()
808 addPass(createLoadStoreVectorizerPass()); in addCodeGenPrepare()
814 addPass(createLowerSwitchPass()); in addCodeGenPrepare()
818 addPass(createFlattenCFGPass()); in addPreISel()
824 addPass(createAMDGPUISelDag(&getAMDGPUTargetMachine(), getOptLevel()), false); in addInstSelector()
841 addPass(createStructurizeCFGPass()); in addPreISel()
846 addPass(createR600ISelDag(&getAMDGPUTargetMachine(), getOptLevel())); in addInstSelector()
851 addPass(createR600VectorRegMerger()); in addPreRegAlloc()
855 addPass(createR600EmitClauseMarkers(), false); in addPreSched2()
857 addPass(&IfConverterID, false); in addPreSched2()
858 addPass(createR600ClauseMergePass(), false); in addPreSched2()
862 addPass(createAMDGPUCFGStructurizerPass(), false); in addPreEmitPass()
863 addPass(createR600ExpandSpecialInstrsPass(), false); in addPreEmitPass()
864 addPass(&FinalizeMachineBundlesID, false); in addPreEmitPass()
865 addPass(createR600Packetizer(), false); in addPreEmitPass()
866 addPass(createR600ControlFlowFinalizer(), false); in addPreEmitPass()
888 addPass(createAMDGPULateCodeGenPreparePass()); in addPreISel()
890 addPass(createAMDGPUAtomicOptimizerPass()); in addPreISel()
898 addPass(&AMDGPUUnifyDivergentExitNodesID); in addPreISel()
901 addPass(createFixIrreduciblePass()); in addPreISel()
902 addPass(createUnifyLoopExitsPass()); in addPreISel()
904 addPass(createStructurizeCFGPass(false)); // true -> SkipUniformRegions in addPreISel()
906 addPass(createSinkingPass()); in addPreISel()
907 addPass(createAMDGPUAnnotateUniformValues()); in addPreISel()
909 addPass(createSIAnnotateControlFlowPass()); in addPreISel()
911 addPass(createLCSSAPass()); in addPreISel()
926 addPass(&SIFoldOperandsID); in addMachineSSAOptimization()
928 addPass(&GCNDPPCombineID); in addMachineSSAOptimization()
929 addPass(&DeadMachineInstructionElimID); in addMachineSSAOptimization()
930 addPass(&SILoadStoreOptimizerID); in addMachineSSAOptimization()
932 addPass(&SIPeepholeSDWAID); in addMachineSSAOptimization()
933 addPass(&EarlyMachineLICMID); in addMachineSSAOptimization()
934 addPass(&MachineCSEID); in addMachineSSAOptimization()
935 addPass(&SIFoldOperandsID); in addMachineSSAOptimization()
936 addPass(&DeadMachineInstructionElimID); in addMachineSSAOptimization()
938 addPass(createSIShrinkInstructionsPass()); in addMachineSSAOptimization()
943 addPass(&EarlyIfConverterID); in addILPOpts()
951 addPass(&SIFixSGPRCopiesID); in addInstSelector()
952 addPass(createSILowerI1CopiesPass()); in addInstSelector()
953 addPass(createSIAddIMGInitPass()); in addInstSelector()
958 addPass(new IRTranslator(getOptLevel())); in addIRTranslator()
964 addPass(createAMDGPUPreLegalizeCombiner(IsOptNone)); in addPreLegalizeMachineIR()
965 addPass(new Localizer()); in addPreLegalizeMachineIR()
969 addPass(new Legalizer()); in addLegalizeMachineIR()
975 addPass(createAMDGPUPostLegalizeCombiner(IsOptNone)); in addPreRegBankSelect()
979 addPass(new RegBankSelect()); in addRegBankSelect()
984 addPass(new InstructionSelect()); in addGlobalInstructionSelect()
990 addPass(createAMDGPUMachineCFGStructurizerPass()); in addPreRegAlloc()
1032 addPass(&GCNNSAReassignID); in addPreRewrite()
1033 addPass(&GCNRegBankReassignID); in addPreRewrite()
1039 addPass(&SIFixVGPRCopiesID); in addPostRegAlloc()
1041 addPass(&SIOptimizeExecMaskingID); in addPostRegAlloc()
1045 addPass(&SILowerSGPRSpillsID); in addPostRegAlloc()
1049 addPass(&SIPostRABundlerID); in addPreSched2()
1053 addPass(createSIMemoryLegalizerPass()); in addPreEmitPass()
1054 addPass(createSIInsertWaitcntsPass()); in addPreEmitPass()
1055 addPass(createSIShrinkInstructionsPass()); in addPreEmitPass()
1056 addPass(createSIModeRegisterPass()); in addPreEmitPass()
1059 addPass(&SIInsertHardClausesID); in addPreEmitPass()
1061 addPass(&SIRemoveShortExecBranchesID); in addPreEmitPass()
1062 addPass(&SIInsertSkipsPassID); in addPreEmitPass()
1063 addPass(&SIPreEmitPeepholeID); in addPreEmitPass()
1072 addPass(&PostRAHazardRecognizerID); in addPreEmitPass()
1073 addPass(&BranchRelaxationPassID); in addPreEmitPass()