Lines Matching refs:AMDGPU
65 using namespace llvm::AMDGPU;
282 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16); in isRegOrImmWithInt16InputMods()
286 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32); in isRegOrImmWithInt32InputMods()
290 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); in isRegOrImmWithInt64InputMods()
294 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); in isRegOrImmWithFP16InputMods()
298 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32); in isRegOrImmWithFP32InputMods()
302 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); in isRegOrImmWithFP64InputMods()
306 return isRegClass(AMDGPU::VGPR_32RegClassID) || in isVReg()
307 isRegClass(AMDGPU::VReg_64RegClassID) || in isVReg()
308 isRegClass(AMDGPU::VReg_96RegClassID) || in isVReg()
309 isRegClass(AMDGPU::VReg_128RegClassID) || in isVReg()
310 isRegClass(AMDGPU::VReg_160RegClassID) || in isVReg()
311 isRegClass(AMDGPU::VReg_192RegClassID) || in isVReg()
312 isRegClass(AMDGPU::VReg_256RegClassID) || in isVReg()
313 isRegClass(AMDGPU::VReg_512RegClassID) || in isVReg()
314 isRegClass(AMDGPU::VReg_1024RegClassID); in isVReg()
318 return isRegClass(AMDGPU::VGPR_32RegClassID); in isVReg32()
326 return isRegKind() && getReg() == AMDGPU::SGPR_NULL; in isNull()
410 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16); in isSCSrcB16()
418 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32); in isSCSrcB32()
422 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); in isSCSrcB64()
428 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); in isSCSrcF16()
436 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32); in isSCSrcF32()
440 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64); in isSCSrcF64()
480 return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) || in isSSrcOrLdsB32()
485 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32); in isVCSrcB32()
489 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); in isVCSrcB64()
493 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16); in isVCSrcB16()
501 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32); in isVCSrcF32()
505 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64); in isVCSrcF64()
509 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); in isVCSrcF16()
549 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32); in isVISrcB32()
553 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16); in isVISrcB16()
561 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32); in isVISrcF32()
565 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16); in isVISrcF16()
573 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32); in isAISrcB32()
577 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16); in isAISrcB16()
585 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32); in isAISrcF32()
589 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16); in isAISrcF16()
597 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32); in isAISrc_128B32()
601 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16); in isAISrc_128B16()
609 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32); in isAISrc_128F32()
613 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16); in isAISrc_128F16()
621 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32); in isAISrc_512B32()
625 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16); in isAISrc_512B16()
633 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32); in isAISrc_512F32()
637 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16); in isAISrc_512F16()
645 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32); in isAISrc_1024B32()
649 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16); in isAISrc_1024B16()
657 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32); in isAISrc_1024F32()
661 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16); in isAISrc_1024F16()
1168 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in AMDGPUAsmParser()
1196 return AMDGPU::hasXNACK(getSTI()); in hasXNACK()
1200 return AMDGPU::hasMIMG_R128(getSTI()); in hasMIMG_R128()
1204 return AMDGPU::hasPackedD16(getSTI()); in hasPackedD16()
1208 return AMDGPU::hasGFX10A16(getSTI()); in hasGFX10A16()
1212 return AMDGPU::isSI(getSTI()); in isSI()
1216 return AMDGPU::isCI(getSTI()); in isCI()
1220 return AMDGPU::isVI(getSTI()); in isVI()
1224 return AMDGPU::isGFX9(getSTI()); in isGFX9()
1228 return AMDGPU::isGFX9Plus(getSTI()); in isGFX9Plus()
1232 return AMDGPU::isGFX10(getSTI()); in isGFX10()
1235 bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); } in isGFX10Plus()
1238 return AMDGPU::isGFX10_BEncoding(getSTI()); in isGFX10_BEncoding()
1242 return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]; in hasInv2PiInlineImm()
1246 return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets]; in hasFlatOffsets()
1256 return getFeatureBits()[AMDGPU::FeatureIntClamp]; in hasIntClamp()
1572 case AMDGPU::OPERAND_REG_IMM_INT32: in getOpFltSemantics()
1573 case AMDGPU::OPERAND_REG_IMM_FP32: in getOpFltSemantics()
1574 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in getOpFltSemantics()
1575 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in getOpFltSemantics()
1576 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in getOpFltSemantics()
1577 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in getOpFltSemantics()
1579 case AMDGPU::OPERAND_REG_IMM_INT64: in getOpFltSemantics()
1580 case AMDGPU::OPERAND_REG_IMM_FP64: in getOpFltSemantics()
1581 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in getOpFltSemantics()
1582 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in getOpFltSemantics()
1584 case AMDGPU::OPERAND_REG_IMM_INT16: in getOpFltSemantics()
1585 case AMDGPU::OPERAND_REG_IMM_FP16: in getOpFltSemantics()
1586 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in getOpFltSemantics()
1587 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in getOpFltSemantics()
1588 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in getOpFltSemantics()
1589 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in getOpFltSemantics()
1590 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in getOpFltSemantics()
1591 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in getOpFltSemantics()
1592 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in getOpFltSemantics()
1593 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in getOpFltSemantics()
1594 case AMDGPU::OPERAND_REG_IMM_V2INT16: in getOpFltSemantics()
1595 case AMDGPU::OPERAND_REG_IMM_V2FP16: in getOpFltSemantics()
1635 return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi); in isInlineableLiteralOp16()
1660 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1675 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1682 return AMDGPU::isInlinableLiteral64(Imm.Val, in isInlinableImm()
1696 return AMDGPU::isInlinableLiteral32( in isInlinableImm()
1756 return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type); in isSDWAOperand()
1778 return (AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || in isBoolReg()
1779 (AsmParser->getFeatureBits()[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()); in isBoolReg()
1800 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), in addImmOperands()
1816 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1819 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1829 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
1830 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
1831 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
1832 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
1833 if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), in addLiteralImmOperand()
1841 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
1859 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
1860 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
1861 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
1862 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
1863 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
1864 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
1865 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
1866 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
1867 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
1868 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
1869 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
1870 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
1871 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
1872 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
1873 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
1874 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: in addLiteralImmOperand()
1875 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
1876 case AMDGPU::OPERAND_REG_IMM_V2FP16: { in addLiteralImmOperand()
1900 case AMDGPU::OPERAND_REG_IMM_INT32: in addLiteralImmOperand()
1901 case AMDGPU::OPERAND_REG_IMM_FP32: in addLiteralImmOperand()
1902 case AMDGPU::OPERAND_REG_INLINE_C_INT32: in addLiteralImmOperand()
1903 case AMDGPU::OPERAND_REG_INLINE_C_FP32: in addLiteralImmOperand()
1904 case AMDGPU::OPERAND_REG_INLINE_AC_INT32: in addLiteralImmOperand()
1905 case AMDGPU::OPERAND_REG_INLINE_AC_FP32: in addLiteralImmOperand()
1906 case AMDGPU::OPERAND_REG_IMM_V2INT16: in addLiteralImmOperand()
1907 case AMDGPU::OPERAND_REG_IMM_V2FP16: in addLiteralImmOperand()
1909 AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), in addLiteralImmOperand()
1920 case AMDGPU::OPERAND_REG_IMM_INT64: in addLiteralImmOperand()
1921 case AMDGPU::OPERAND_REG_IMM_FP64: in addLiteralImmOperand()
1922 case AMDGPU::OPERAND_REG_INLINE_C_INT64: in addLiteralImmOperand()
1923 case AMDGPU::OPERAND_REG_INLINE_C_FP64: in addLiteralImmOperand()
1924 if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { in addLiteralImmOperand()
1934 case AMDGPU::OPERAND_REG_IMM_INT16: in addLiteralImmOperand()
1935 case AMDGPU::OPERAND_REG_IMM_FP16: in addLiteralImmOperand()
1936 case AMDGPU::OPERAND_REG_INLINE_C_INT16: in addLiteralImmOperand()
1937 case AMDGPU::OPERAND_REG_INLINE_C_FP16: in addLiteralImmOperand()
1938 case AMDGPU::OPERAND_REG_INLINE_AC_INT16: in addLiteralImmOperand()
1939 case AMDGPU::OPERAND_REG_INLINE_AC_FP16: in addLiteralImmOperand()
1941 AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
1952 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: in addLiteralImmOperand()
1953 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: in addLiteralImmOperand()
1954 case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: in addLiteralImmOperand()
1955 case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { in addLiteralImmOperand()
1957 assert(AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), in addLiteralImmOperand()
1987 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); in addRegOperands()
1992 case AMDGPU::SRC_SHARED_BASE: in isInlineValue()
1993 case AMDGPU::SRC_SHARED_LIMIT: in isInlineValue()
1994 case AMDGPU::SRC_PRIVATE_BASE: in isInlineValue()
1995 case AMDGPU::SRC_PRIVATE_LIMIT: in isInlineValue()
1996 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in isInlineValue()
1998 case AMDGPU::SRC_VCCZ: in isInlineValue()
1999 case AMDGPU::SRC_EXECZ: in isInlineValue()
2000 case AMDGPU::SRC_SCC: in isInlineValue()
2002 case AMDGPU::SGPR_NULL: in isInlineValue()
2021 case 1: return AMDGPU::VGPR_32RegClassID; in getRegClass()
2022 case 2: return AMDGPU::VReg_64RegClassID; in getRegClass()
2023 case 3: return AMDGPU::VReg_96RegClassID; in getRegClass()
2024 case 4: return AMDGPU::VReg_128RegClassID; in getRegClass()
2025 case 5: return AMDGPU::VReg_160RegClassID; in getRegClass()
2026 case 6: return AMDGPU::VReg_192RegClassID; in getRegClass()
2027 case 8: return AMDGPU::VReg_256RegClassID; in getRegClass()
2028 case 16: return AMDGPU::VReg_512RegClassID; in getRegClass()
2029 case 32: return AMDGPU::VReg_1024RegClassID; in getRegClass()
2034 case 1: return AMDGPU::TTMP_32RegClassID; in getRegClass()
2035 case 2: return AMDGPU::TTMP_64RegClassID; in getRegClass()
2036 case 4: return AMDGPU::TTMP_128RegClassID; in getRegClass()
2037 case 8: return AMDGPU::TTMP_256RegClassID; in getRegClass()
2038 case 16: return AMDGPU::TTMP_512RegClassID; in getRegClass()
2043 case 1: return AMDGPU::SGPR_32RegClassID; in getRegClass()
2044 case 2: return AMDGPU::SGPR_64RegClassID; in getRegClass()
2045 case 3: return AMDGPU::SGPR_96RegClassID; in getRegClass()
2046 case 4: return AMDGPU::SGPR_128RegClassID; in getRegClass()
2047 case 5: return AMDGPU::SGPR_160RegClassID; in getRegClass()
2048 case 6: return AMDGPU::SGPR_192RegClassID; in getRegClass()
2049 case 8: return AMDGPU::SGPR_256RegClassID; in getRegClass()
2050 case 16: return AMDGPU::SGPR_512RegClassID; in getRegClass()
2055 case 1: return AMDGPU::AGPR_32RegClassID; in getRegClass()
2056 case 2: return AMDGPU::AReg_64RegClassID; in getRegClass()
2057 case 3: return AMDGPU::AReg_96RegClassID; in getRegClass()
2058 case 4: return AMDGPU::AReg_128RegClassID; in getRegClass()
2059 case 5: return AMDGPU::AReg_160RegClassID; in getRegClass()
2060 case 6: return AMDGPU::AReg_192RegClassID; in getRegClass()
2061 case 8: return AMDGPU::AReg_256RegClassID; in getRegClass()
2062 case 16: return AMDGPU::AReg_512RegClassID; in getRegClass()
2063 case 32: return AMDGPU::AReg_1024RegClassID; in getRegClass()
2071 .Case("exec", AMDGPU::EXEC) in getSpecialRegForName()
2072 .Case("vcc", AMDGPU::VCC) in getSpecialRegForName()
2073 .Case("flat_scratch", AMDGPU::FLAT_SCR) in getSpecialRegForName()
2074 .Case("xnack_mask", AMDGPU::XNACK_MASK) in getSpecialRegForName()
2075 .Case("shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2076 .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE) in getSpecialRegForName()
2077 .Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2078 .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT) in getSpecialRegForName()
2079 .Case("private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2080 .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE) in getSpecialRegForName()
2081 .Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2082 .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT) in getSpecialRegForName()
2083 .Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2084 .Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) in getSpecialRegForName()
2085 .Case("lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2086 .Case("src_lds_direct", AMDGPU::LDS_DIRECT) in getSpecialRegForName()
2087 .Case("m0", AMDGPU::M0) in getSpecialRegForName()
2088 .Case("vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2089 .Case("src_vccz", AMDGPU::SRC_VCCZ) in getSpecialRegForName()
2090 .Case("execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2091 .Case("src_execz", AMDGPU::SRC_EXECZ) in getSpecialRegForName()
2092 .Case("scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2093 .Case("src_scc", AMDGPU::SRC_SCC) in getSpecialRegForName()
2094 .Case("tba", AMDGPU::TBA) in getSpecialRegForName()
2095 .Case("tma", AMDGPU::TMA) in getSpecialRegForName()
2096 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) in getSpecialRegForName()
2097 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) in getSpecialRegForName()
2098 .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO) in getSpecialRegForName()
2099 .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI) in getSpecialRegForName()
2100 .Case("vcc_lo", AMDGPU::VCC_LO) in getSpecialRegForName()
2101 .Case("vcc_hi", AMDGPU::VCC_HI) in getSpecialRegForName()
2102 .Case("exec_lo", AMDGPU::EXEC_LO) in getSpecialRegForName()
2103 .Case("exec_hi", AMDGPU::EXEC_HI) in getSpecialRegForName()
2104 .Case("tma_lo", AMDGPU::TMA_LO) in getSpecialRegForName()
2105 .Case("tma_hi", AMDGPU::TMA_HI) in getSpecialRegForName()
2106 .Case("tba_lo", AMDGPU::TBA_LO) in getSpecialRegForName()
2107 .Case("tba_hi", AMDGPU::TBA_HI) in getSpecialRegForName()
2108 .Case("pc", AMDGPU::PC_REG) in getSpecialRegForName()
2109 .Case("null", AMDGPU::SGPR_NULL) in getSpecialRegForName()
2110 .Default(AMDGPU::NoRegister); in getSpecialRegForName()
2148 if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { in AddNextRegisterToList()
2149 Reg = AMDGPU::EXEC; in AddNextRegisterToList()
2153 if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { in AddNextRegisterToList()
2154 Reg = AMDGPU::FLAT_SCR; in AddNextRegisterToList()
2158 if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) { in AddNextRegisterToList()
2159 Reg = AMDGPU::XNACK_MASK; in AddNextRegisterToList()
2163 if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { in AddNextRegisterToList()
2164 Reg = AMDGPU::VCC; in AddNextRegisterToList()
2168 if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { in AddNextRegisterToList()
2169 Reg = AMDGPU::TBA; in AddNextRegisterToList()
2173 if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { in AddNextRegisterToList()
2174 Reg = AMDGPU::TMA; in AddNextRegisterToList()
2256 return getSpecialRegForName(Str) != AMDGPU::NoRegister; in isRegister()
2282 return AMDGPU::NoRegister; in getRegularReg()
2289 return AMDGPU::NoRegister; in getRegularReg()
2296 return AMDGPU::NoRegister; in getRegularReg()
2370 return AMDGPU::NoRegister; in ParseRegularReg()
2382 return AMDGPU::NoRegister; in ParseRegularReg()
2388 return AMDGPU::NoRegister; in ParseRegularReg()
2397 unsigned Reg = AMDGPU::NoRegister; in ParseRegList()
2402 return AMDGPU::NoRegister; in ParseRegList()
2409 return AMDGPU::NoRegister; in ParseRegList()
2412 return AMDGPU::NoRegister; in ParseRegList()
2423 return AMDGPU::NoRegister; in ParseRegList()
2427 return AMDGPU::NoRegister; in ParseRegList()
2431 return AMDGPU::NoRegister; in ParseRegList()
2434 return AMDGPU::NoRegister; in ParseRegList()
2439 return AMDGPU::NoRegister; in ParseRegList()
2452 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2456 if (Reg == AMDGPU::NoRegister) in ParseAMDGPURegister()
2463 if (Reg == AMDGPU::NoRegister) { in ParseAMDGPURegister()
2469 if (Reg == AMDGPU::SGPR_NULL) { in ParseAMDGPURegister()
2483 Reg = AMDGPU::NoRegister; in ParseAMDGPURegister()
2520 if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6) in updateGprCountSymbols()
2900 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in checkTargetMatchPredicate()
2901 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in checkTargetMatchPredicate()
2904 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel); in checkTargetMatchPredicate()
2906 if (!Op.isImm() || Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) { in checkTargetMatchPredicate()
2971 case AMDGPU::FLAT_SCR: in findImplicitSGPRReadInVOP()
2972 case AMDGPU::VCC: in findImplicitSGPRReadInVOP()
2973 case AMDGPU::VCC_LO: in findImplicitSGPRReadInVOP()
2974 case AMDGPU::VCC_HI: in findImplicitSGPRReadInVOP()
2975 case AMDGPU::M0: in findImplicitSGPRReadInVOP()
2981 return AMDGPU::NoRegister; in findImplicitSGPRReadInVOP()
2992 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) { in isInlineConstant()
2999 auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx); in isInlineConstant()
3003 return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm()); in isInlineConstant()
3005 return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm()); in isInlineConstant()
3008 if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 || in isInlineConstant()
3009 OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 || in isInlineConstant()
3010 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16) in isInlineConstant()
3011 return AMDGPU::isInlinableIntLiteral(Val); in isInlineConstant()
3013 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 || in isInlineConstant()
3014 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 || in isInlineConstant()
3015 OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16) in isInlineConstant()
3016 return AMDGPU::isInlinableIntLiteralV216(Val); in isInlineConstant()
3018 if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 || in isInlineConstant()
3019 OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 || in isInlineConstant()
3020 OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16) in isInlineConstant()
3021 return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm()); in isInlineConstant()
3023 return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm()); in isInlineConstant()
3036 case AMDGPU::V_LSHLREV_B64: in getConstantBusLimit()
3037 case AMDGPU::V_LSHLREV_B64_gfx10: in getConstantBusLimit()
3038 case AMDGPU::V_LSHL_B64: in getConstantBusLimit()
3039 case AMDGPU::V_LSHRREV_B64: in getConstantBusLimit()
3040 case AMDGPU::V_LSHRREV_B64_gfx10: in getConstantBusLimit()
3041 case AMDGPU::V_LSHR_B64: in getConstantBusLimit()
3042 case AMDGPU::V_ASHRREV_I64: in getConstantBusLimit()
3043 case AMDGPU::V_ASHRREV_I64_gfx10: in getConstantBusLimit()
3044 case AMDGPU::V_ASHR_I64: in getConstantBusLimit()
3070 unsigned LastSGPR = AMDGPU::NoRegister; in validateConstantBusLimitations()
3081 if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) { in validateConstantBusLimitations()
3087 if (SGPRUsed != AMDGPU::NoRegister) { in validateConstantBusLimitations()
3092 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateConstantBusLimitations()
3093 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateConstantBusLimitations()
3094 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateConstantBusLimitations()
3129 unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx); in validateConstantBusLimitations()
3160 const int DstIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::vdst); in validateEarlyClobberLimitations()
3168 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateEarlyClobberLimitations()
3169 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateEarlyClobberLimitations()
3170 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateEarlyClobberLimitations()
3201 int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp); in validateIntClampSupported()
3217 int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata); in validateMIMGDataSize()
3218 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGDataSize()
3219 int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe); in validateMIMGDataSize()
3226 unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx); in validateMIMGDataSize()
3235 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGDataSize()
3250 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc); in validateMIMGAddrSize()
3252 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in validateMIMGAddrSize()
3253 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in validateMIMGAddrSize()
3254 int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); in validateMIMGAddrSize()
3255 int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); in validateMIMGAddrSize()
3256 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGAddrSize()
3266 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim); in validateMIMGAddrSize()
3270 : AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4; in validateMIMGAddrSize()
3296 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGAtomicDMask()
3314 int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask); in validateMIMGGatherDMask()
3328 case AMDGPU::V_MOVRELS_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3329 case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3330 case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10: in IsMovrelsSDWAOpcode()
3349 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMovrels()
3373 if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi) in validateMAIAccWrite()
3376 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0); in validateMAIAccWrite()
3409 for (auto Name : {AMDGPU::OpName::src0_modifiers, in validateDivScale()
3410 AMDGPU::OpName::src2_modifiers, in validateDivScale()
3411 AMDGPU::OpName::src2_modifiers}) { in validateDivScale()
3412 if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name)) in validateDivScale()
3430 int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16); in validateMIMGD16()
3446 int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim); in validateMIMGDim()
3460 case AMDGPU::V_SUBREV_F32_e32: in IsRevOpcode()
3461 case AMDGPU::V_SUBREV_F32_e64: in IsRevOpcode()
3462 case AMDGPU::V_SUBREV_F32_e32_gfx10: in IsRevOpcode()
3463 case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7: in IsRevOpcode()
3464 case AMDGPU::V_SUBREV_F32_e32_vi: in IsRevOpcode()
3465 case AMDGPU::V_SUBREV_F32_e64_gfx10: in IsRevOpcode()
3466 case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7: in IsRevOpcode()
3467 case AMDGPU::V_SUBREV_F32_e64_vi: in IsRevOpcode()
3469 case AMDGPU::V_SUBREV_CO_U32_e32: in IsRevOpcode()
3470 case AMDGPU::V_SUBREV_CO_U32_e64: in IsRevOpcode()
3471 case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
3472 case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
3474 case AMDGPU::V_SUBBREV_U32_e32: in IsRevOpcode()
3475 case AMDGPU::V_SUBBREV_U32_e64: in IsRevOpcode()
3476 case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7: in IsRevOpcode()
3477 case AMDGPU::V_SUBBREV_U32_e32_vi: in IsRevOpcode()
3478 case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7: in IsRevOpcode()
3479 case AMDGPU::V_SUBBREV_U32_e64_vi: in IsRevOpcode()
3481 case AMDGPU::V_SUBREV_U32_e32: in IsRevOpcode()
3482 case AMDGPU::V_SUBREV_U32_e64: in IsRevOpcode()
3483 case AMDGPU::V_SUBREV_U32_e32_gfx9: in IsRevOpcode()
3484 case AMDGPU::V_SUBREV_U32_e32_vi: in IsRevOpcode()
3485 case AMDGPU::V_SUBREV_U32_e64_gfx9: in IsRevOpcode()
3486 case AMDGPU::V_SUBREV_U32_e64_vi: in IsRevOpcode()
3488 case AMDGPU::V_SUBREV_F16_e32: in IsRevOpcode()
3489 case AMDGPU::V_SUBREV_F16_e64: in IsRevOpcode()
3490 case AMDGPU::V_SUBREV_F16_e32_gfx10: in IsRevOpcode()
3491 case AMDGPU::V_SUBREV_F16_e32_vi: in IsRevOpcode()
3492 case AMDGPU::V_SUBREV_F16_e64_gfx10: in IsRevOpcode()
3493 case AMDGPU::V_SUBREV_F16_e64_vi: in IsRevOpcode()
3495 case AMDGPU::V_SUBREV_U16_e32: in IsRevOpcode()
3496 case AMDGPU::V_SUBREV_U16_e64: in IsRevOpcode()
3497 case AMDGPU::V_SUBREV_U16_e32_vi: in IsRevOpcode()
3498 case AMDGPU::V_SUBREV_U16_e64_vi: in IsRevOpcode()
3500 case AMDGPU::V_SUBREV_CO_U32_e32_gfx9: in IsRevOpcode()
3501 case AMDGPU::V_SUBREV_CO_U32_e64_gfx10: in IsRevOpcode()
3502 case AMDGPU::V_SUBREV_CO_U32_e64_gfx9: in IsRevOpcode()
3504 case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9: in IsRevOpcode()
3505 case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9: in IsRevOpcode()
3507 case AMDGPU::V_SUBREV_NC_U32_e32_gfx10: in IsRevOpcode()
3508 case AMDGPU::V_SUBREV_NC_U32_e64_gfx10: in IsRevOpcode()
3510 case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: in IsRevOpcode()
3511 case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10: in IsRevOpcode()
3513 case AMDGPU::V_LSHRREV_B32_e32: in IsRevOpcode()
3514 case AMDGPU::V_LSHRREV_B32_e64: in IsRevOpcode()
3515 case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
3516 case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
3517 case AMDGPU::V_LSHRREV_B32_e32_vi: in IsRevOpcode()
3518 case AMDGPU::V_LSHRREV_B32_e64_vi: in IsRevOpcode()
3519 case AMDGPU::V_LSHRREV_B32_e32_gfx10: in IsRevOpcode()
3520 case AMDGPU::V_LSHRREV_B32_e64_gfx10: in IsRevOpcode()
3522 case AMDGPU::V_ASHRREV_I32_e32: in IsRevOpcode()
3523 case AMDGPU::V_ASHRREV_I32_e64: in IsRevOpcode()
3524 case AMDGPU::V_ASHRREV_I32_e32_gfx10: in IsRevOpcode()
3525 case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7: in IsRevOpcode()
3526 case AMDGPU::V_ASHRREV_I32_e32_vi: in IsRevOpcode()
3527 case AMDGPU::V_ASHRREV_I32_e64_gfx10: in IsRevOpcode()
3528 case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7: in IsRevOpcode()
3529 case AMDGPU::V_ASHRREV_I32_e64_vi: in IsRevOpcode()
3531 case AMDGPU::V_LSHLREV_B32_e32: in IsRevOpcode()
3532 case AMDGPU::V_LSHLREV_B32_e64: in IsRevOpcode()
3533 case AMDGPU::V_LSHLREV_B32_e32_gfx10: in IsRevOpcode()
3534 case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7: in IsRevOpcode()
3535 case AMDGPU::V_LSHLREV_B32_e32_vi: in IsRevOpcode()
3536 case AMDGPU::V_LSHLREV_B32_e64_gfx10: in IsRevOpcode()
3537 case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7: in IsRevOpcode()
3538 case AMDGPU::V_LSHLREV_B32_e64_vi: in IsRevOpcode()
3540 case AMDGPU::V_LSHLREV_B16_e32: in IsRevOpcode()
3541 case AMDGPU::V_LSHLREV_B16_e64: in IsRevOpcode()
3542 case AMDGPU::V_LSHLREV_B16_e32_vi: in IsRevOpcode()
3543 case AMDGPU::V_LSHLREV_B16_e64_vi: in IsRevOpcode()
3544 case AMDGPU::V_LSHLREV_B16_gfx10: in IsRevOpcode()
3546 case AMDGPU::V_LSHRREV_B16_e32: in IsRevOpcode()
3547 case AMDGPU::V_LSHRREV_B16_e64: in IsRevOpcode()
3548 case AMDGPU::V_LSHRREV_B16_e32_vi: in IsRevOpcode()
3549 case AMDGPU::V_LSHRREV_B16_e64_vi: in IsRevOpcode()
3550 case AMDGPU::V_LSHRREV_B16_gfx10: in IsRevOpcode()
3552 case AMDGPU::V_ASHRREV_I16_e32: in IsRevOpcode()
3553 case AMDGPU::V_ASHRREV_I16_e64: in IsRevOpcode()
3554 case AMDGPU::V_ASHRREV_I16_e32_vi: in IsRevOpcode()
3555 case AMDGPU::V_ASHRREV_I16_e64_vi: in IsRevOpcode()
3556 case AMDGPU::V_ASHRREV_I16_gfx10: in IsRevOpcode()
3558 case AMDGPU::V_LSHLREV_B64: in IsRevOpcode()
3559 case AMDGPU::V_LSHLREV_B64_gfx10: in IsRevOpcode()
3560 case AMDGPU::V_LSHLREV_B64_vi: in IsRevOpcode()
3562 case AMDGPU::V_LSHRREV_B64: in IsRevOpcode()
3563 case AMDGPU::V_LSHRREV_B64_gfx10: in IsRevOpcode()
3564 case AMDGPU::V_LSHRREV_B64_vi: in IsRevOpcode()
3566 case AMDGPU::V_ASHRREV_I64: in IsRevOpcode()
3567 case AMDGPU::V_ASHRREV_I64_gfx10: in IsRevOpcode()
3568 case AMDGPU::V_ASHRREV_I64_vi: in IsRevOpcode()
3570 case AMDGPU::V_PK_LSHLREV_B16: in IsRevOpcode()
3571 case AMDGPU::V_PK_LSHLREV_B16_gfx10: in IsRevOpcode()
3572 case AMDGPU::V_PK_LSHLREV_B16_vi: in IsRevOpcode()
3574 case AMDGPU::V_PK_LSHRREV_B16: in IsRevOpcode()
3575 case AMDGPU::V_PK_LSHRREV_B16_gfx10: in IsRevOpcode()
3576 case AMDGPU::V_PK_LSHRREV_B16_vi: in IsRevOpcode()
3577 case AMDGPU::V_PK_ASHRREV_I16: in IsRevOpcode()
3578 case AMDGPU::V_PK_ASHRREV_I16_gfx10: in IsRevOpcode()
3579 case AMDGPU::V_PK_ASHRREV_I16_vi: in IsRevOpcode()
3597 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateLdsDirect()
3598 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateLdsDirect()
3599 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateLdsDirect()
3639 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateFlatOffset()
3692 auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset); in validateSMEMOffset()
3701 bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode); in validateSMEMOffset()
3702 if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) || in validateSMEMOffset()
3703 AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer)) in validateSMEMOffset()
3719 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateSOPLiteral()
3720 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateSOPLiteral()
3733 if (AMDGPU::isSISrcOperand(Desc, OpIdx)) { in validateSOPLiteral()
3751 if (Opc == AMDGPU::V_PERMLANE16_B32_gfx10 || in validateOpSel()
3752 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10) { in validateOpSel()
3753 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in validateOpSel()
3765 return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) || in validateVccOperand()
3766 (FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO); in validateVccOperand()
3777 const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0); in validateVOP3Literal()
3778 const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1); in validateVOP3Literal()
3779 const int Src2Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2); in validateVOP3Literal()
3793 if (!AMDGPU::isSISrcOperand(Desc, OpIdx)) in validateVOP3Literal()
3797 getFeatureBits()[AMDGPU::FeatureMFMAInlineLiteralBug]) { in validateVOP3Literal()
3818 if (!getFeatureBits()[AMDGPU::FeatureVOP3Literal]) { in validateVOP3Literal()
3834 int GLCPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), in validateCoherencyBits()
3835 AMDGPU::OpName::glc1); in validateCoherencyBits()
3852 Error(getRegLoc(AMDGPU::LDS_DIRECT, Operands), in validateInstruction()
4464 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in ParseDirectiveHSACodeObjectISA()
4526 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
4529 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
4538 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) in ParseAMDKernelCodeTValue()
4541 if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64]) in ParseAMDKernelCodeTValue()
4569 AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI()); in ParseDirectiveAMDKernelCodeT()
4712 if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin, in ParseDirectivePALMetadataBegin()
4713 AMDGPU::PALMD::AssemblerDirectiveEnd, String)) in ParseDirectivePALMetadataBegin()
4770 unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI()); in ParseDirectiveAMDGPULDS()
4820 if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) in ParseDirective()
4838 if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin) in ParseDirective()
4857 for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true); in subtargetHasRegister()
4864 for (MCRegAliasIterator R(AMDGPU::SGPR104_SGPR105, &MRI, true); in subtargetHasRegister()
4871 case AMDGPU::SRC_SHARED_BASE: in subtargetHasRegister()
4872 case AMDGPU::SRC_SHARED_LIMIT: in subtargetHasRegister()
4873 case AMDGPU::SRC_PRIVATE_BASE: in subtargetHasRegister()
4874 case AMDGPU::SRC_PRIVATE_LIMIT: in subtargetHasRegister()
4875 case AMDGPU::SRC_POPS_EXITING_WAVE_ID: in subtargetHasRegister()
4877 case AMDGPU::TBA: in subtargetHasRegister()
4878 case AMDGPU::TBA_LO: in subtargetHasRegister()
4879 case AMDGPU::TBA_HI: in subtargetHasRegister()
4880 case AMDGPU::TMA: in subtargetHasRegister()
4881 case AMDGPU::TMA_LO: in subtargetHasRegister()
4882 case AMDGPU::TMA_HI: in subtargetHasRegister()
4884 case AMDGPU::XNACK_MASK: in subtargetHasRegister()
4885 case AMDGPU::XNACK_MASK_LO: in subtargetHasRegister()
4886 case AMDGPU::XNACK_MASK_HI: in subtargetHasRegister()
4888 case AMDGPU::SGPR_NULL: in subtargetHasRegister()
4902 case AMDGPU::FLAT_SCR: in subtargetHasRegister()
4903 case AMDGPU::FLAT_SCR_LO: in subtargetHasRegister()
4904 case AMDGPU::FLAT_SCR_HI: in subtargetHasRegister()
4913 for (MCRegAliasIterator R(AMDGPU::SGPR102_SGPR103, &MRI, true); in subtargetHasRegister()
5217 using namespace llvm::AMDGPU::MTBUFFormat; in parseDfmtNfmt()
5250 using namespace llvm::AMDGPU::MTBUFFormat; in parseUfmt()
5268 using namespace llvm::AMDGPU::MTBUFFormat; in matchDfmtNfmt()
5291 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicSplitFormat()
5335 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicUnifiedFormat()
5352 using namespace llvm::AMDGPU::MTBUFFormat; in parseNumericFormat()
5367 using namespace llvm::AMDGPU::MTBUFFormat; in parseSymbolicOrNumericFormat()
5395 using namespace llvm::AMDGPU::MTBUFFormat; in parseFORMAT()
5472 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSOffset01()
5498 (Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx10 || in cvtDSImpl()
5499 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7 || in cvtDSImpl()
5500 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle : in cvtDSImpl()
5508 Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0 in cvtDSImpl()
5533 Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister)); in cvtExp()
5556 Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister); in cvtExp()
5557 Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister); in cvtExp()
5561 if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) { in cvtExp()
5578 const AMDGPU::IsaVersion ISA, in encodeCnt()
5612 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseCnt()
5648 AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); in parseSWaitCntOps()
5679 using namespace llvm::AMDGPU::Hwreg; in parseHwregBody()
5715 using namespace llvm::AMDGPU::Hwreg; in validateHwreg()
5741 using namespace llvm::AMDGPU::Hwreg; in parseHwreg()
5781 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgBody()
5816 using namespace llvm::AMDGPU::SendMsg; in validateSendMsg()
5852 using namespace llvm::AMDGPU::SendMsg; in parseSendMsgOp()
6235 using namespace llvm::AMDGPU::Swizzle; in encodeBitmaskPerm()
6280 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleQuadPerm()
6296 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBroadcast()
6324 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleReverse()
6346 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleSwap()
6368 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleBitmaskPerm()
6430 using namespace llvm::AMDGPU::Swizzle; in parseSwizzleMacro()
6494 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMacro()
6539 using namespace llvm::AMDGPU::VGPRIndexMode; in parseGPRIdxMode()
6685 int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode()); in cvtMubufImpl()
7016 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3OpSel()
7017 AMDGPU::OpName::src1, in cvtVOP3OpSel()
7018 AMDGPU::OpName::src2 }; in cvtVOP3OpSel()
7020 SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1; in cvtVOP3OpSel()
7024 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3OpSel()
7028 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers); in cvtVOP3OpSel()
7036 return Desc.OpInfo[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS in isRegOrImmWithInputMods()
7071 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) { in cvtVOP3Interp()
7075 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3Interp()
7079 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3Interp()
7094 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) { in cvtVOP3()
7120 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) { in cvtVOP3()
7124 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) { in cvtVOP3()
7132 if (Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || in cvtVOP3()
7133 Opc == AMDGPU::V_MAC_F32_e64_gfx10 || in cvtVOP3()
7134 Opc == AMDGPU::V_MAC_F32_e64_vi || in cvtVOP3()
7135 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || in cvtVOP3()
7136 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || in cvtVOP3()
7137 Opc == AMDGPU::V_MAC_F16_e64_vi || in cvtVOP3()
7138 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 || in cvtVOP3()
7139 Opc == AMDGPU::V_FMAC_F32_e64_vi || in cvtVOP3()
7140 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || in cvtVOP3()
7141 Opc == AMDGPU::V_FMAC_F16_e64_gfx10) { in cvtVOP3()
7143 std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers)); in cvtVOP3()
7166 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) { in cvtVOP3P()
7176 int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi); in cvtVOP3P()
7183 int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo); in cvtVOP3P()
7190 const int Ops[] = { AMDGPU::OpName::src0, in cvtVOP3P()
7191 AMDGPU::OpName::src1, in cvtVOP3P()
7192 AMDGPU::OpName::src2 }; in cvtVOP3P()
7193 const int ModOps[] = { AMDGPU::OpName::src0_modifiers, in cvtVOP3P()
7194 AMDGPU::OpName::src1_modifiers, in cvtVOP3P()
7195 AMDGPU::OpName::src2_modifiers }; in cvtVOP3P()
7197 int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel); in cvtVOP3P()
7209 int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi); in cvtVOP3P()
7215 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]); in cvtVOP3P()
7233 int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); in cvtVOP3P()
7248 using namespace AMDGPU::DPP; in isDPPCtrl()
7330 const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId); in parseDim()
7399 using namespace AMDGPU::DPP; in parseDPPCtrl()
7586 using namespace llvm::AMDGPU::DPP; in cvtDPP()
7592 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) { in cvtDPP()
7605 using namespace llvm::AMDGPU::SDWA; in parseSDWASel()
7638 using namespace llvm::AMDGPU::SDWA; in parseSDWADstUnused()
7689 using namespace llvm::AMDGPU::SDWA; in cvtSDWA()
7704 (Op.getReg() == AMDGPU::VCC || Op.getReg() == AMDGPU::VCC_LO)) { in cvtSDWA()
7732 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 && in cvtSDWA()
7733 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 && in cvtSDWA()
7734 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) { in cvtSDWA()
7739 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
7749 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) { in cvtSDWA()
7759 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1) in cvtSDWA()
7772 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi || in cvtSDWA()
7773 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) { in cvtSDWA()
7776 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2)); in cvtSDWA()