Lines Matching refs:Reg
79 : Reg(r), SubReg(s), Mask(m) {} in OperandMask()
80 Register Reg; member in __anondebd7f180111::GCNRegBankReassign::OperandMask
89 : MI(mi), Reg(reg), SubReg(subreg), FreeBanks(freebanks) {} in Candidate()
94 dbgs() << P->printReg(Reg) << " to banks "; in dump()
101 Register Reg; member in __anondebd7f180111::GCNRegBankReassign::Candidate
184 unsigned getPhysRegBank(Register Reg, unsigned SubReg) const;
190 uint32_t getRegBankMask(Register Reg, unsigned SubReg, int Bank);
197 Register Reg = Register(),
202 bool isReassignable(Register Reg) const;
219 unsigned getFreeBanks(Register Reg, unsigned SubReg, unsigned Mask,
231 void removeCandidates(Register Reg);
237 Register Reg = Register(),
255 Printable printReg(Register Reg, unsigned SubReg = 0) const { in printReg() argument
256 return Printable([Reg, SubReg, this](raw_ostream &OS) { in printReg()
257 if (Reg.isPhysical()) { in printReg()
258 OS << llvm::printReg(Reg, TRI); in printReg()
261 if (!VRM->isAssignedReg(Reg)) in printReg()
262 OS << "<unassigned> " << llvm::printReg(Reg, TRI); in printReg()
264 OS << llvm::printReg(Reg, TRI) << '(' in printReg()
265 << llvm::printReg(VRM->getPhys(Reg), TRI) << ')'; in printReg()
301 unsigned GCNRegBankReassign::getPhysRegBank(Register Reg, in getPhysRegBank() argument
303 assert(Reg.isPhysical()); in getPhysRegBank()
305 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getPhysRegBank()
308 Reg = TRI->get32BitRegister(Reg); in getPhysRegBank()
312 Reg = TRI->getSubReg(Reg, SubReg); in getPhysRegBank()
314 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
316 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getPhysRegBank()
321 unsigned RegNo = Reg - AMDGPU::VGPR0; in getPhysRegBank()
325 unsigned RegNo = TRI->getEncodingValue(AMDGPU::getMCReg(Reg, *ST)) / 2; in getPhysRegBank()
329 uint32_t GCNRegBankReassign::getRegBankMask(Register Reg, unsigned SubReg, in getRegBankMask() argument
331 if (Reg.isVirtual()) { in getRegBankMask()
332 if (!VRM->isAssignedReg(Reg)) in getRegBankMask()
335 Reg = VRM->getPhys(Reg); in getRegBankMask()
336 if (!Reg) in getRegBankMask()
339 Reg = TRI->getSubReg(Reg, SubReg); in getRegBankMask()
342 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getRegBankMask()
346 Reg = TRI->get32BitRegister(Reg); in getRegBankMask()
351 Reg = TRI->getSubReg(Reg, AMDGPU::sub0); in getRegBankMask()
356 unsigned RegNo = Reg - AMDGPU::VGPR0; in getRegBankMask()
370 unsigned RegNo = TRI->getEncodingValue(AMDGPU::getMCReg(Reg, *ST)) / 2; in getRegBankMask()
392 GCNRegBankReassign::analyzeInst(const MachineInstr &MI, Register Reg, in analyzeInst() argument
429 if (Bank != -1 && R == Reg && (Op.getSubReg() || SubReg)) { in analyzeInst()
445 (Reg == R) ? ShiftedBank : -1); in analyzeInst()
476 bool GCNRegBankReassign::isReassignable(Register Reg) const { in isReassignable()
477 if (Reg.isPhysical() || !VRM->isAssignedReg(Reg)) in isReassignable()
480 const MachineInstr *Def = MRI->getUniqueVRegDef(Reg); in isReassignable()
482 Register PhysReg = VRM->getPhys(Reg); in isReassignable()
487 for (auto U : MRI->use_nodbg_operands(Reg)) { in isReassignable()
552 unsigned GCNRegBankReassign::getFreeBanks(Register Reg, in getFreeBanks() argument
556 if (!isReassignable(Reg)) in getFreeBanks()
580 dbgs() << "Potential reassignments of " << printReg(Reg, SubReg) in getFreeBanks()
602 Register Reg1 = OperandMasks[I].Reg; in collectCandidates()
603 Register Reg2 = OperandMasks[J].Reg; in collectCandidates()
631 unsigned GCNRegBankReassign::computeStallCycles(Register SrcReg, Register Reg, in computeStallCycles() argument
644 std::tie(StallCycles, UsedBanks) = analyzeInst(MI, Reg, SubReg, Bank); in computeStallCycles()
661 for (MCRegister Reg : RC->getRegisters()) { in scavengeReg() local
663 if (TRI->isSubRegisterEq(Reg, MaxReg)) in scavengeReg()
666 if (!MRI->isAllocatable(Reg) || getPhysRegBank(Reg, SubReg) != Bank) in scavengeReg()
670 if (TRI->isSubRegisterEq(Reg, CSRegs[I]) && in scavengeReg()
674 LLVM_DEBUG(dbgs() << "Trying register " << printReg(Reg) << '\n'); in scavengeReg()
676 if (!LRM->checkInterference(LI, Reg)) in scavengeReg()
677 return Reg; in scavengeReg()
684 if (!LIS->hasInterval(C.Reg)) in tryReassign()
687 LiveInterval &LI = LIS->getInterval(C.Reg); in tryReassign()
688 LLVM_DEBUG(dbgs() << "Try reassign " << printReg(C.Reg) << " in "; C.MI->dump(); in tryReassign()
695 unsigned OrigStalls = computeStallCycles(C.Reg); in tryReassign()
715 unsigned Stalls = computeStallCycles(C.Reg, C.Reg, C.SubReg, Bank); in tryReassign()
725 MCRegister OrigReg = VRM->getPhys(C.Reg); in tryReassign()
729 MCRegister Reg = scavengeReg(LI, BS.Bank, C.SubReg); in tryReassign() local
730 if (Reg == AMDGPU::NoRegister) { in tryReassign()
735 LLVM_DEBUG(dbgs() << "Found free register " << printReg(Reg) in tryReassign()
736 << (LRM->isPhysRegUsed(Reg) ? "" : " (new)") in tryReassign()
739 LRM->assign(LI, Reg); in tryReassign()
781 void GCNRegBankReassign::removeCandidates(Register Reg) { in removeCandidates() argument
785 I->second.remove_if([Reg, this](const Candidate& C) { in removeCandidates()
786 return C.MI->readsRegister(Reg, TRI); in removeCandidates()
849 removeCandidates(C.Reg); in runOnMachineFunction()
850 computeStallCycles(C.Reg, AMDGPU::NoRegister, 0, -1, true); in runOnMachineFunction()