Lines Matching refs:DL
508 SDLoc DL(Op); in LowerOperation() local
514 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
515 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
516 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
517 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
519 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
532 SDLoc DL(Op); in LowerOperation() local
549 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
551 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
552 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
553 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
554 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
558 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
559 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
560 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
561 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
569 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
574 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
576 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
578 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
580 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
582 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
584 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
586 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
587 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
588 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
590 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
596 return DAG.getConstant(ByteOffset, DL, PtrVT); in LowerOperation()
599 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
601 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
603 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
605 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
607 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
609 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
611 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
613 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
615 return LowerImplicitParameter(DAG, VT, DL, 8); in LowerOperation()
643 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
646 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
702 SDLoc DL(Vector); in vectorToVerticalVector() local
708 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
709 DAG.getVectorIdxConstant(i, DL))); in vectorToVerticalVector()
712 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
717 SDLoc DL(Op); in LowerEXTRACT_VECTOR_ELT() local
726 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
732 SDLoc DL(Op); in LowerINSERT_VECTOR_ELT() local
742 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
754 const DataLayout &DL = DAG.getDataLayout(); in LowerGlobalAddress() local
756 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
767 SDLoc DL(Op); in LowerTrig() local
770 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
771 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
772 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
773 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
774 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
786 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
787 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
788 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
792 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
793 DAG.getConstantFP(numbers::pif, DL, MVT::f32)); in LowerTrig()
797 SDLoc DL(Op); in LowerSHLParts() local
803 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSHLParts()
804 SDValue One = DAG.getConstant(1, DL, VT); in LowerSHLParts()
806 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSHLParts()
807 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts()
808 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSHLParts()
809 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
816 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
817 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
819 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
820 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow); in LowerSHLParts()
821 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
823 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
826 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSHLParts()
827 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
829 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
833 SDLoc DL(Op); in LowerSRXParts() local
839 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerSRXParts()
840 SDValue One = DAG.getConstant(1, DL, VT); in LowerSRXParts()
844 SDValue Width = DAG.getConstant(VT.getSizeInBits(), DL, VT); in LowerSRXParts()
845 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts()
846 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSRXParts()
847 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
854 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
855 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
857 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
858 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
859 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); in LowerSRXParts()
861 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
862 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
864 Hi = DAG.getSelectCC(DL, Shift, Width, HiSmall, HiBig, ISD::SETULT); in LowerSRXParts()
865 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
867 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
872 SDLoc DL(Op); in LowerUADDSUBO() local
878 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
880 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
883 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
885 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
889 SDLoc DL(Op); in lowerFP_TO_UINT() local
892 DL, in lowerFP_TO_UINT()
894 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
899 SDLoc DL(Op); in lowerFP_TO_SINT() local
902 DL, in lowerFP_TO_SINT()
904 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
909 const SDLoc &DL, in LowerImplicitParameter() argument
918 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
919 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
948 SDLoc DL(Op); in LowerSELECT_CC() local
960 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
999 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1040 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
1041 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
1056 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1060 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1068 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT); in LowerSELECT_CC()
1069 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT); in LowerSELECT_CC()
1071 HWTrue = DAG.getConstant(-1, DL, CompareVT); in LowerSELECT_CC()
1072 HWFalse = DAG.getConstant(0, DL, CompareVT); in LowerSELECT_CC()
1080 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1082 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1110 SDLoc DL(Ptr); in stackPtrToRegIndex() local
1111 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1112 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1146 SDLoc DL(Store); in lowerPrivateTruncStore() local
1155 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1158 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1173 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1178 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1179 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1184 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1189 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1190 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1193 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1194 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1198 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1202 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1205 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1209 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1213 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1216 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1219 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1223 SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo); in lowerPrivateTruncStore()
1228 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1246 SDLoc DL(Op); in LowerSTORE() local
1256 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1259 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), in LowerSTORE()
1276 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1277 DAG.getConstant(2, DL, PtrVT)); in LowerSTORE()
1286 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1290 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1293 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1294 DAG.getConstant(0x00000003, DL, PtrVT)); in LowerSTORE()
1295 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1296 DAG.getConstant(3, DL, VT)); in LowerSTORE()
1299 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1302 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1303 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1309 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1310 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1313 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1315 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL, in LowerSTORE()
1320 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1325 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1341 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1342 return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1392 SDLoc DL(Op); in lowerPrivateExtLoad() local
1404 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1409 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1410 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1415 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1418 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1419 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1422 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1423 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1426 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1433 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1435 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
1443 return DAG.getMergeValues(Ops, DL); in lowerPrivateExtLoad()
1457 SDLoc DL(Op); in LowerLOAD() local
1467 return DAG.getMergeValues(Ops, DL); in LowerLOAD()
1482 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1483 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1484 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1486 AMDGPUAS::CONSTANT_BUFFER_0, DL, MVT::i32) in LowerLOAD()
1491 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1492 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1499 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1512 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
1514 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1518 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1528 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1529 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1530 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1586 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
1612 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
1642 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1643 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1654 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType() argument
1694 SDLoc DL(VectorEntry); in CompactSwizzlableVector() local
1699 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1700 DAG.getIntPtrConstant(i, DL)); in CompactSwizzlableVector()
1738 SDLoc DL(VectorEntry); in ReorganizeVector() local
1744 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1745 DAG.getIntPtrConstant(i, DL)); in ReorganizeVector()
1776 const SDLoc &DL) const { in OptimizeSwizzle()
1784 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1792 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1800 SDLoc DL(LoadNode); in constBufferLoad() local
1822 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1823 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1824 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1832 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements)); in constBufferLoad()
1834 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1835 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1841 return DAG.getMergeValues(MergedValues, DL); in constBufferLoad()
1851 SDLoc DL(N); in PerformDAGCombine() local
1858 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1883 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1886 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1887 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
1934 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1935 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1940 return DAG.getBuildVector(VT, DL, Ops); in PerformDAGCombine()
1959 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
2000 return DAG.getSelectCC(DL, in PerformDAGCombine()
2027 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL); in PerformDAGCombine()
2028 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2056 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL); in PerformDAGCombine()
2057 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()