Lines Matching refs:LiveRegs
39 LivePhysRegs &LiveRegs, in findScratchNonCalleeSaveRegister() argument
45 LiveRegs.addReg(CSRegs[i]); in findScratchNonCalleeSaveRegister()
51 if (!MRI.isPhysRegUsed(Reg) && LiveRegs.available(MRI, Reg)) in findScratchNonCalleeSaveRegister()
56 if (LiveRegs.available(MRI, Reg)) in findScratchNonCalleeSaveRegister()
71 LivePhysRegs &LiveRegs, in getVGPRSpillLaneOrTempRegister() argument
105 MF.getRegInfo(), LiveRegs, AMDGPU::SReg_32_XM0_XEXECRegClass, true); in getVGPRSpillLaneOrTempRegister()
137 static void buildPrologSpill(const GCNSubtarget &ST, LivePhysRegs &LiveRegs, in buildPrologSpill() argument
180 LiveRegs.addReg(SpillReg); in buildPrologSpill()
184 MF->getRegInfo(), LiveRegs, AMDGPU::SReg_32_XM0RegClass); in buildPrologSpill()
200 MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass); in buildPrologSpill()
219 LiveRegs.removeReg(SpillReg); in buildPrologSpill()
222 static void buildEpilogReload(const GCNSubtarget &ST, LivePhysRegs &LiveRegs, in buildEpilogReload() argument
248 MF->getRegInfo(), LiveRegs, AMDGPU::SReg_32_XM0RegClass); in buildEpilogReload()
280 MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass); in buildEpilogReload()
348 LivePhysRegs LiveRegs; in emitEntryFunctionFlatScratchInit() local
349 LiveRegs.init(*TRI); in emitEntryFunctionFlatScratchInit()
350 LiveRegs.addLiveIns(MBB); in emitEntryFunctionFlatScratchInit()
361 if (LiveRegs.available(MRI, Reg) && MRI.isAllocatable(Reg) && in emitEntryFunctionFlatScratchInit()
797 static Register buildScratchExecCopy(LivePhysRegs &LiveRegs, in buildScratchExecCopy() argument
810 if (LiveRegs.empty()) { in buildScratchExecCopy()
812 LiveRegs.init(TRI); in buildScratchExecCopy()
813 LiveRegs.addLiveIns(MBB); in buildScratchExecCopy()
815 LiveRegs.removeReg(FuncInfo->SGPRForFPSaveRestoreCopy); in buildScratchExecCopy()
818 LiveRegs.removeReg(FuncInfo->SGPRForBPSaveRestoreCopy); in buildScratchExecCopy()
821 LiveRegs.init(*ST.getRegisterInfo()); in buildScratchExecCopy()
822 LiveRegs.addLiveOuts(MBB); in buildScratchExecCopy()
823 LiveRegs.stepBackward(*MBBI); in buildScratchExecCopy()
828 MRI, LiveRegs, *TRI.getWaveMaskRegClass()); in buildScratchExecCopy()
831 LiveRegs.removeReg(ScratchExecCopy); in buildScratchExecCopy()
858 LivePhysRegs LiveRegs; in emitPrologue() local
928 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true); in emitPrologue()
930 buildPrologSpill(ST, LiveRegs, MBB, MBBI, TII, Reg.VGPR, in emitPrologue()
940 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true); in emitPrologue()
943 MRI, LiveRegs, AMDGPU::VGPR_32RegClass); in emitPrologue()
948 buildPrologSpill(ST, LiveRegs, MBB, MBBI, TII, TmpVGPR, in emitPrologue()
957 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, true); in emitPrologue()
960 MRI, LiveRegs, AMDGPU::VGPR_32RegClass); in emitPrologue()
965 buildPrologSpill(ST, LiveRegs, MBB, MBBI, TII, TmpVGPR, in emitPrologue()
976 LiveRegs.addReg(ScratchExecCopy); in emitPrologue()
1020 if (LiveRegs.empty()) { in emitPrologue()
1021 LiveRegs.init(TRI); in emitPrologue()
1022 LiveRegs.addLiveIns(MBB); in emitPrologue()
1023 LiveRegs.addReg(FuncInfo->SGPRForFPSaveRestoreCopy); in emitPrologue()
1024 LiveRegs.addReg(FuncInfo->SGPRForBPSaveRestoreCopy); in emitPrologue()
1028 MRI, LiveRegs, AMDGPU::SReg_32_XM0RegClass); in emitPrologue()
1094 LivePhysRegs LiveRegs; in emitEpilogue() local
1146 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false); in emitEpilogue()
1149 MRI, LiveRegs, AMDGPU::VGPR_32RegClass); in emitEpilogue()
1150 buildEpilogReload(ST, LiveRegs, MBB, MBBI, TII, TempVGPR, in emitEpilogue()
1171 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false); in emitEpilogue()
1174 MRI, LiveRegs, AMDGPU::VGPR_32RegClass); in emitEpilogue()
1175 buildEpilogReload(ST, LiveRegs, MBB, MBBI, TII, TempVGPR, in emitEpilogue()
1197 ScratchExecCopy = buildScratchExecCopy(LiveRegs, MF, MBB, MBBI, false); in emitEpilogue()
1199 buildEpilogReload(ST, LiveRegs, MBB, MBBI, TII, Reg.VGPR, in emitEpilogue()
1305 LivePhysRegs LiveRegs; in determineCalleeSaves() local
1306 LiveRegs.init(*TRI); in determineCalleeSaves()
1309 getVGPRSpillLaneOrTempRegister(MF, LiveRegs, MFI->SGPRForFPSaveRestoreCopy, in determineCalleeSaves()
1315 LiveRegs.addReg(MFI->SGPRForFPSaveRestoreCopy); in determineCalleeSaves()
1316 getVGPRSpillLaneOrTempRegister(MF, LiveRegs, MFI->SGPRForBPSaveRestoreCopy, in determineCalleeSaves()