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Lines Matching refs:STM

186                const GCNSubtarget &STM);
205 const GCNSubtarget *STM = nullptr; member in __anonbd440fb60111::SILoadStoreOptimizer
502 const GCNSubtarget &STM) { in setMI() argument
522 EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4); in setMI()
848 bool SILoadStoreOptimizer::widthsFit(const GCNSubtarget &STM, in widthsFit() argument
854 return (Width <= 4) && (STM.hasDwordx3LoadStores() || (Width != 3)); in widthsFit()
877 (!widthsFit(*STM, CI, Paired) || !offsetsCanBeCombined(CI, *STM, Paired))) in checkAndPrepareMerge()
976 offsetsCanBeCombined(CI, *STM, Paired, true); in checkAndPrepareMerge()
995 if (STM->ldsRequiresM0Init()) in read2Opcode()
1001 if (STM->ldsRequiresM0Init()) in read2ST64Opcode()
1093 if (STM->ldsRequiresM0Init()) in write2Opcode()
1100 if (STM->ldsRequiresM0Init()) in write2ST64Opcode()
1366 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM); in mergeTBufferLoadPair()
1446 getBufferFormatWithCompCount(CI.Format, CI.Width + Paired.Width, *STM); in mergeTBufferStorePair()
1876 static_cast<const SITargetLowering *>(STM->getTargetLowering()); in promoteConstantOffsetToImm()
1994 CI.setMI(MI, *TII, *STM); in collectMergeableInsts()
2107 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2113 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2119 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2126 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2133 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2140 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2147 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2154 CI.setMI(NewMI, *TII, *STM); in optimizeInstsWithSameBaseAddr()
2173 STM = &MF.getSubtarget<GCNSubtarget>(); in runOnMachineFunction()
2174 if (!STM->loadStoreOptEnabled()) in runOnMachineFunction()
2177 TII = STM->getInstrInfo(); in runOnMachineFunction()