Lines Matching refs:DstReg
95 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
514 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesFromI1() local
519 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
526 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); in lowerCopiesFromI1()
530 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in lowerCopiesFromI1()
574 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
575 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
600 PhiRegisters.insert(DstReg); in lowerPhis()
606 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerPhis()
613 SSAUpdater.Initialize(DstReg); in lowerPhis()
661 if (NewReg != DstReg) { in lowerPhis()
662 MRI->replaceRegWith(NewReg, DstReg); in lowerPhis()
685 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesToI1() local
686 if (!isVreg1(DstReg)) in lowerCopiesToI1()
689 if (MRI->use_empty(DstReg)) { in lowerCopiesToI1()
696 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
718 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerCopiesToI1()
725 SSAUpdater.Initialize(DstReg); in lowerCopiesToI1()
726 SSAUpdater.AddAvailableValue(&MBB, DstReg); in lowerCopiesToI1()
729 buildMergeLaneMasks(MBB, MI, DL, DstReg, in lowerCopiesToI1()
819 const DebugLoc &DL, unsigned DstReg, in buildMergeLaneMasks() argument
828 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg); in buildMergeLaneMasks()
830 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg); in buildMergeLaneMasks()
832 BuildMI(MBB, I, DL, TII->get(XorOp), DstReg) in buildMergeLaneMasks()
864 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg) in buildMergeLaneMasks()
867 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg) in buildMergeLaneMasks()
870 BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg) in buildMergeLaneMasks()
874 BuildMI(MBB, I, DL, TII->get(OrOp), DstReg) in buildMergeLaneMasks()