Lines Matching refs:AMDGPU
53 : AMDGPUGenRegisterInfo(AMDGPU::PC_REG, ST.getAMDGPUDwarfFlavour()), ST(ST), in SIRegisterInfo()
56 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && in SIRegisterInfo()
57 getSubRegIndexLaneMask(AMDGPU::sub31).getAsInteger() == (3ULL << 62) && in SIRegisterInfo()
58 (getSubRegIndexLaneMask(AMDGPU::lo16) | in SIRegisterInfo()
59 getSubRegIndexLaneMask(AMDGPU::hi16)).getAsInteger() == in SIRegisterInfo()
60 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && in SIRegisterInfo()
65 *MCRegUnitIterator(MCRegister::from(AMDGPU::M0), this)); in SIRegisterInfo()
66 for (auto Reg : AMDGPU::VGPR_HI16RegClass) in SIRegisterInfo()
94 Row.fill(AMDGPU::NoSubRegister); in SIRegisterInfo()
134 static const MCPhysReg NoCalleeSavedReg = AMDGPU::NoRegister; in getCalleeSavedRegs()
184 Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; } in getBaseRegister()
206 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg()
207 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SGPR_128RegClass); in reservedPrivateSegmentBufferReg()
212 Reserved.set(AMDGPU::MODE); in getReservedRegs()
216 reserveRegisterTuples(Reserved, AMDGPU::EXEC); in getReservedRegs()
217 reserveRegisterTuples(Reserved, AMDGPU::FLAT_SCR); in getReservedRegs()
220 reserveRegisterTuples(Reserved, AMDGPU::M0); in getReservedRegs()
223 reserveRegisterTuples(Reserved, AMDGPU::SRC_VCCZ); in getReservedRegs()
224 reserveRegisterTuples(Reserved, AMDGPU::SRC_EXECZ); in getReservedRegs()
225 reserveRegisterTuples(Reserved, AMDGPU::SRC_SCC); in getReservedRegs()
228 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_BASE); in getReservedRegs()
229 reserveRegisterTuples(Reserved, AMDGPU::SRC_SHARED_LIMIT); in getReservedRegs()
230 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_BASE); in getReservedRegs()
231 reserveRegisterTuples(Reserved, AMDGPU::SRC_PRIVATE_LIMIT); in getReservedRegs()
234 reserveRegisterTuples(Reserved, AMDGPU::SRC_POPS_EXITING_WAVE_ID); in getReservedRegs()
237 reserveRegisterTuples(Reserved, AMDGPU::XNACK_MASK); in getReservedRegs()
240 reserveRegisterTuples(Reserved, AMDGPU::LDS_DIRECT); in getReservedRegs()
243 reserveRegisterTuples(Reserved, AMDGPU::TBA); in getReservedRegs()
244 reserveRegisterTuples(Reserved, AMDGPU::TMA); in getReservedRegs()
245 reserveRegisterTuples(Reserved, AMDGPU::TTMP0_TTMP1); in getReservedRegs()
246 reserveRegisterTuples(Reserved, AMDGPU::TTMP2_TTMP3); in getReservedRegs()
247 reserveRegisterTuples(Reserved, AMDGPU::TTMP4_TTMP5); in getReservedRegs()
248 reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7); in getReservedRegs()
249 reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9); in getReservedRegs()
250 reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11); in getReservedRegs()
251 reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13); in getReservedRegs()
252 reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15); in getReservedRegs()
255 reserveRegisterTuples(Reserved, AMDGPU::SGPR_NULL); in getReservedRegs()
260 Reserved.set(AMDGPU::VCC); in getReservedRegs()
261 Reserved.set(AMDGPU::VCC_HI); in getReservedRegs()
265 unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs(); in getReservedRegs()
267 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i); in getReservedRegs()
272 unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs(); in getReservedRegs()
274 unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i); in getReservedRegs()
276 Reg = AMDGPU::AGPR_32RegClass.getRegister(i); in getReservedRegs()
280 for (auto Reg : AMDGPU::SReg_32RegClass) { in getReservedRegs()
281 Reserved.set(getSubReg(Reg, AMDGPU::hi16)); in getReservedRegs()
282 Register Low = getSubReg(Reg, AMDGPU::lo16); in getReservedRegs()
284 if (!AMDGPU::SGPR_LO16RegClass.contains(Low)) in getReservedRegs()
288 for (auto Reg : AMDGPU::AGPR_32RegClass) { in getReservedRegs()
289 Reserved.set(getSubReg(Reg, AMDGPU::hi16)); in getReservedRegs()
295 unsigned Reg = AMDGPU::AGPR_32RegClass.getRegister(i); in getReservedRegs()
303 if (ScratchRSrcReg != AMDGPU::NoRegister) { in getReservedRegs()
397 int OffIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getScratchInstrOffset()
398 AMDGPU::OpName::offset); in getScratchInstrOffset()
407 assert((Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
408 AMDGPU::OpName::vaddr) || in getFrameIndexInstrOffset()
409 (Idx == AMDGPU::getNamedOperandIdx(MI->getOpcode(), in getFrameIndexInstrOffset()
410 AMDGPU::OpName::saddr))) && in getFrameIndexInstrOffset()
441 unsigned MovOpc = ST.enableFlatScratch() ? AMDGPU::S_MOV_B32 in materializeFrameBaseRegister()
442 : AMDGPU::V_MOV_B32_e32; in materializeFrameBaseRegister()
451 Register OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass); in materializeFrameBaseRegister()
454 ST.enableFlatScratch() ? &AMDGPU::SReg_32_XM0RegClass in materializeFrameBaseRegister()
455 : &AMDGPU::VGPR_32RegClass); in materializeFrameBaseRegister()
457 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
463 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_U32), BaseReg) in materializeFrameBaseRegister()
494 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
495 : AMDGPU::OpName::vaddr); in resolveFrameIndex()
497 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
514 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
548 return &AMDGPU::VGPR_32RegClass; in getPointerRegClass()
554 case AMDGPU::SI_SPILL_S1024_SAVE: in getNumSubRegsForSpillOp()
555 case AMDGPU::SI_SPILL_S1024_RESTORE: in getNumSubRegsForSpillOp()
556 case AMDGPU::SI_SPILL_V1024_SAVE: in getNumSubRegsForSpillOp()
557 case AMDGPU::SI_SPILL_V1024_RESTORE: in getNumSubRegsForSpillOp()
558 case AMDGPU::SI_SPILL_A1024_SAVE: in getNumSubRegsForSpillOp()
559 case AMDGPU::SI_SPILL_A1024_RESTORE: in getNumSubRegsForSpillOp()
561 case AMDGPU::SI_SPILL_S512_SAVE: in getNumSubRegsForSpillOp()
562 case AMDGPU::SI_SPILL_S512_RESTORE: in getNumSubRegsForSpillOp()
563 case AMDGPU::SI_SPILL_V512_SAVE: in getNumSubRegsForSpillOp()
564 case AMDGPU::SI_SPILL_V512_RESTORE: in getNumSubRegsForSpillOp()
565 case AMDGPU::SI_SPILL_A512_SAVE: in getNumSubRegsForSpillOp()
566 case AMDGPU::SI_SPILL_A512_RESTORE: in getNumSubRegsForSpillOp()
568 case AMDGPU::SI_SPILL_S256_SAVE: in getNumSubRegsForSpillOp()
569 case AMDGPU::SI_SPILL_S256_RESTORE: in getNumSubRegsForSpillOp()
570 case AMDGPU::SI_SPILL_V256_SAVE: in getNumSubRegsForSpillOp()
571 case AMDGPU::SI_SPILL_V256_RESTORE: in getNumSubRegsForSpillOp()
572 case AMDGPU::SI_SPILL_A256_SAVE: in getNumSubRegsForSpillOp()
573 case AMDGPU::SI_SPILL_A256_RESTORE: in getNumSubRegsForSpillOp()
575 case AMDGPU::SI_SPILL_S192_SAVE: in getNumSubRegsForSpillOp()
576 case AMDGPU::SI_SPILL_S192_RESTORE: in getNumSubRegsForSpillOp()
577 case AMDGPU::SI_SPILL_V192_SAVE: in getNumSubRegsForSpillOp()
578 case AMDGPU::SI_SPILL_V192_RESTORE: in getNumSubRegsForSpillOp()
579 case AMDGPU::SI_SPILL_A192_SAVE: in getNumSubRegsForSpillOp()
580 case AMDGPU::SI_SPILL_A192_RESTORE: in getNumSubRegsForSpillOp()
582 case AMDGPU::SI_SPILL_S160_SAVE: in getNumSubRegsForSpillOp()
583 case AMDGPU::SI_SPILL_S160_RESTORE: in getNumSubRegsForSpillOp()
584 case AMDGPU::SI_SPILL_V160_SAVE: in getNumSubRegsForSpillOp()
585 case AMDGPU::SI_SPILL_V160_RESTORE: in getNumSubRegsForSpillOp()
586 case AMDGPU::SI_SPILL_A160_SAVE: in getNumSubRegsForSpillOp()
587 case AMDGPU::SI_SPILL_A160_RESTORE: in getNumSubRegsForSpillOp()
589 case AMDGPU::SI_SPILL_S128_SAVE: in getNumSubRegsForSpillOp()
590 case AMDGPU::SI_SPILL_S128_RESTORE: in getNumSubRegsForSpillOp()
591 case AMDGPU::SI_SPILL_V128_SAVE: in getNumSubRegsForSpillOp()
592 case AMDGPU::SI_SPILL_V128_RESTORE: in getNumSubRegsForSpillOp()
593 case AMDGPU::SI_SPILL_A128_SAVE: in getNumSubRegsForSpillOp()
594 case AMDGPU::SI_SPILL_A128_RESTORE: in getNumSubRegsForSpillOp()
596 case AMDGPU::SI_SPILL_S96_SAVE: in getNumSubRegsForSpillOp()
597 case AMDGPU::SI_SPILL_S96_RESTORE: in getNumSubRegsForSpillOp()
598 case AMDGPU::SI_SPILL_V96_SAVE: in getNumSubRegsForSpillOp()
599 case AMDGPU::SI_SPILL_V96_RESTORE: in getNumSubRegsForSpillOp()
600 case AMDGPU::SI_SPILL_A96_SAVE: in getNumSubRegsForSpillOp()
601 case AMDGPU::SI_SPILL_A96_RESTORE: in getNumSubRegsForSpillOp()
603 case AMDGPU::SI_SPILL_S64_SAVE: in getNumSubRegsForSpillOp()
604 case AMDGPU::SI_SPILL_S64_RESTORE: in getNumSubRegsForSpillOp()
605 case AMDGPU::SI_SPILL_V64_SAVE: in getNumSubRegsForSpillOp()
606 case AMDGPU::SI_SPILL_V64_RESTORE: in getNumSubRegsForSpillOp()
607 case AMDGPU::SI_SPILL_A64_SAVE: in getNumSubRegsForSpillOp()
608 case AMDGPU::SI_SPILL_A64_RESTORE: in getNumSubRegsForSpillOp()
610 case AMDGPU::SI_SPILL_S32_SAVE: in getNumSubRegsForSpillOp()
611 case AMDGPU::SI_SPILL_S32_RESTORE: in getNumSubRegsForSpillOp()
612 case AMDGPU::SI_SPILL_V32_SAVE: in getNumSubRegsForSpillOp()
613 case AMDGPU::SI_SPILL_V32_RESTORE: in getNumSubRegsForSpillOp()
614 case AMDGPU::SI_SPILL_A32_SAVE: in getNumSubRegsForSpillOp()
615 case AMDGPU::SI_SPILL_A32_RESTORE: in getNumSubRegsForSpillOp()
623 case AMDGPU::BUFFER_STORE_DWORD_OFFEN: in getOffsetMUBUFStore()
624 return AMDGPU::BUFFER_STORE_DWORD_OFFSET; in getOffsetMUBUFStore()
625 case AMDGPU::BUFFER_STORE_BYTE_OFFEN: in getOffsetMUBUFStore()
626 return AMDGPU::BUFFER_STORE_BYTE_OFFSET; in getOffsetMUBUFStore()
627 case AMDGPU::BUFFER_STORE_SHORT_OFFEN: in getOffsetMUBUFStore()
628 return AMDGPU::BUFFER_STORE_SHORT_OFFSET; in getOffsetMUBUFStore()
629 case AMDGPU::BUFFER_STORE_DWORDX2_OFFEN: in getOffsetMUBUFStore()
630 return AMDGPU::BUFFER_STORE_DWORDX2_OFFSET; in getOffsetMUBUFStore()
631 case AMDGPU::BUFFER_STORE_DWORDX4_OFFEN: in getOffsetMUBUFStore()
632 return AMDGPU::BUFFER_STORE_DWORDX4_OFFSET; in getOffsetMUBUFStore()
633 case AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN: in getOffsetMUBUFStore()
634 return AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET; in getOffsetMUBUFStore()
635 case AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN: in getOffsetMUBUFStore()
636 return AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET; in getOffsetMUBUFStore()
644 case AMDGPU::BUFFER_LOAD_DWORD_OFFEN: in getOffsetMUBUFLoad()
645 return AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in getOffsetMUBUFLoad()
646 case AMDGPU::BUFFER_LOAD_UBYTE_OFFEN: in getOffsetMUBUFLoad()
647 return AMDGPU::BUFFER_LOAD_UBYTE_OFFSET; in getOffsetMUBUFLoad()
648 case AMDGPU::BUFFER_LOAD_SBYTE_OFFEN: in getOffsetMUBUFLoad()
649 return AMDGPU::BUFFER_LOAD_SBYTE_OFFSET; in getOffsetMUBUFLoad()
650 case AMDGPU::BUFFER_LOAD_USHORT_OFFEN: in getOffsetMUBUFLoad()
651 return AMDGPU::BUFFER_LOAD_USHORT_OFFSET; in getOffsetMUBUFLoad()
652 case AMDGPU::BUFFER_LOAD_SSHORT_OFFEN: in getOffsetMUBUFLoad()
653 return AMDGPU::BUFFER_LOAD_SSHORT_OFFSET; in getOffsetMUBUFLoad()
654 case AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN: in getOffsetMUBUFLoad()
655 return AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET; in getOffsetMUBUFLoad()
656 case AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN: in getOffsetMUBUFLoad()
657 return AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET; in getOffsetMUBUFLoad()
658 case AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
659 return AMDGPU::BUFFER_LOAD_UBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
660 case AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
661 return AMDGPU::BUFFER_LOAD_UBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
662 case AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFEN: in getOffsetMUBUFLoad()
663 return AMDGPU::BUFFER_LOAD_SBYTE_D16_OFFSET; in getOffsetMUBUFLoad()
664 case AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFEN: in getOffsetMUBUFLoad()
665 return AMDGPU::BUFFER_LOAD_SBYTE_D16_HI_OFFSET; in getOffsetMUBUFLoad()
666 case AMDGPU::BUFFER_LOAD_SHORT_D16_OFFEN: in getOffsetMUBUFLoad()
667 return AMDGPU::BUFFER_LOAD_SHORT_D16_OFFSET; in getOffsetMUBUFLoad()
668 case AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFEN: in getOffsetMUBUFLoad()
669 return AMDGPU::BUFFER_LOAD_SHORT_D16_HI_OFFSET; in getOffsetMUBUFLoad()
688 if (Reg == AMDGPU::NoRegister) in spillVGPRtoAGPR()
697 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32 in spillVGPRtoAGPR()
698 : AMDGPU::V_ACCVGPR_READ_B32; in spillVGPRtoAGPR()
724 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
731 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
732 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
742 AMDGPU::OpName::vdata_in); in buildMUBUFOffsetLoadStore()
773 unsigned NumSubRegs = AMDGPU::getRegBitWidth(RC->getID()) / (EltSize * CHAR_BIT); in buildSpillLoadStore()
799 SOffset = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0, false); in buildSpillLoadStore()
820 if (ScratchOffsetReg == AMDGPU::NoRegister) { in buildSpillLoadStore()
821 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), SOffset) in buildSpillLoadStore()
824 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset) in buildSpillLoadStore()
832 if (IsFlat && SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
833 assert(AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) < 0 in buildSpillLoadStore()
837 LoadStoreOp = AMDGPU::getFlatScratchInstSTfromSS(LoadStoreOp); in buildSpillLoadStore()
872 TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in buildSpillLoadStore()
877 TII->get(AMDGPU::V_ACCVGPR_READ_B32), TmpReg) in buildSpillLoadStore()
897 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
915 if (!IsStore && TmpReg != AMDGPU::NoRegister) { in buildSpillLoadStore()
916 MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), in buildSpillLoadStore()
933 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), SOffset) in buildSpillLoadStore()
965 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in buildSGPRSpillLoadStore()
966 SuperReg != AMDGPU::EXEC && "exec should never spill"); in buildSGPRSpillLoadStore()
970 bool OnlyExecLo = isWave32 || NumSubRegs == 1 || SuperReg == AMDGPU::EXEC_HI; in buildSGPRSpillLoadStore()
972 unsigned ExecMovOpc = OnlyExecLo ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in buildSGPRSpillLoadStore()
973 Register ExecReg = OnlyExecLo ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in buildSGPRSpillLoadStore()
986 getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]), AMDGPU::sub0, in buildSGPRSpillLoadStore()
987 &AMDGPU::SReg_64_XEXECRegClass); in buildSGPRSpillLoadStore()
1014 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in buildSGPRSpillLoadStore()
1015 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in buildSGPRSpillLoadStore()
1023 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in buildSGPRSpillLoadStore()
1024 : AMDGPU::BUFFER_STORE_DWORD_OFFSET; in buildSGPRSpillLoadStore()
1042 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), in buildSGPRSpillLoadStore()
1047 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), in buildSGPRSpillLoadStore()
1080 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in spillSGPR()
1081 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in spillSGPR()
1082 SuperReg != AMDGPU::EXEC && "exec should never spill"); in spillSGPR()
1109 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill.VGPR) in spillSGPR()
1130 Register TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in spillSGPR()
1152 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), TmpVGPR) in spillSGPR()
1199 assert(SuperReg != AMDGPU::M0 && "m0 should never spill"); in restoreSGPR()
1200 assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI && in restoreSGPR()
1201 SuperReg != AMDGPU::EXEC && "exec should never spill"); in restoreSGPR()
1217 auto MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1224 Register TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in restoreSGPR()
1246 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg) in restoreSGPR()
1267 case AMDGPU::SI_SPILL_S1024_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1268 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1269 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1270 case AMDGPU::SI_SPILL_S192_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1271 case AMDGPU::SI_SPILL_S160_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1272 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1273 case AMDGPU::SI_SPILL_S96_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1274 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1275 case AMDGPU::SI_SPILL_S32_SAVE: in eliminateSGPRToVGPRSpillFrameIndex()
1277 case AMDGPU::SI_SPILL_S1024_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1278 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1279 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1280 case AMDGPU::SI_SPILL_S192_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1281 case AMDGPU::SI_SPILL_S160_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1282 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1283 case AMDGPU::SI_SPILL_S96_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1284 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1285 case AMDGPU::SI_SPILL_S32_RESTORE: in eliminateSGPRToVGPRSpillFrameIndex()
1313 case AMDGPU::SI_SPILL_S1024_SAVE: in eliminateFrameIndex()
1314 case AMDGPU::SI_SPILL_S512_SAVE: in eliminateFrameIndex()
1315 case AMDGPU::SI_SPILL_S256_SAVE: in eliminateFrameIndex()
1316 case AMDGPU::SI_SPILL_S192_SAVE: in eliminateFrameIndex()
1317 case AMDGPU::SI_SPILL_S160_SAVE: in eliminateFrameIndex()
1318 case AMDGPU::SI_SPILL_S128_SAVE: in eliminateFrameIndex()
1319 case AMDGPU::SI_SPILL_S96_SAVE: in eliminateFrameIndex()
1320 case AMDGPU::SI_SPILL_S64_SAVE: in eliminateFrameIndex()
1321 case AMDGPU::SI_SPILL_S32_SAVE: { in eliminateFrameIndex()
1327 case AMDGPU::SI_SPILL_S1024_RESTORE: in eliminateFrameIndex()
1328 case AMDGPU::SI_SPILL_S512_RESTORE: in eliminateFrameIndex()
1329 case AMDGPU::SI_SPILL_S256_RESTORE: in eliminateFrameIndex()
1330 case AMDGPU::SI_SPILL_S192_RESTORE: in eliminateFrameIndex()
1331 case AMDGPU::SI_SPILL_S160_RESTORE: in eliminateFrameIndex()
1332 case AMDGPU::SI_SPILL_S128_RESTORE: in eliminateFrameIndex()
1333 case AMDGPU::SI_SPILL_S96_RESTORE: in eliminateFrameIndex()
1334 case AMDGPU::SI_SPILL_S64_RESTORE: in eliminateFrameIndex()
1335 case AMDGPU::SI_SPILL_S32_RESTORE: { in eliminateFrameIndex()
1341 case AMDGPU::SI_SPILL_V1024_SAVE: in eliminateFrameIndex()
1342 case AMDGPU::SI_SPILL_V512_SAVE: in eliminateFrameIndex()
1343 case AMDGPU::SI_SPILL_V256_SAVE: in eliminateFrameIndex()
1344 case AMDGPU::SI_SPILL_V160_SAVE: in eliminateFrameIndex()
1345 case AMDGPU::SI_SPILL_V128_SAVE: in eliminateFrameIndex()
1346 case AMDGPU::SI_SPILL_V96_SAVE: in eliminateFrameIndex()
1347 case AMDGPU::SI_SPILL_V64_SAVE: in eliminateFrameIndex()
1348 case AMDGPU::SI_SPILL_V32_SAVE: in eliminateFrameIndex()
1349 case AMDGPU::SI_SPILL_A1024_SAVE: in eliminateFrameIndex()
1350 case AMDGPU::SI_SPILL_A512_SAVE: in eliminateFrameIndex()
1351 case AMDGPU::SI_SPILL_A256_SAVE: in eliminateFrameIndex()
1352 case AMDGPU::SI_SPILL_A192_SAVE: in eliminateFrameIndex()
1353 case AMDGPU::SI_SPILL_A160_SAVE: in eliminateFrameIndex()
1354 case AMDGPU::SI_SPILL_A128_SAVE: in eliminateFrameIndex()
1355 case AMDGPU::SI_SPILL_A96_SAVE: in eliminateFrameIndex()
1356 case AMDGPU::SI_SPILL_A64_SAVE: in eliminateFrameIndex()
1357 case AMDGPU::SI_SPILL_A32_SAVE: { in eliminateFrameIndex()
1359 AMDGPU::OpName::vdata); in eliminateFrameIndex()
1360 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1363 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_STORE_DWORD_SADDR in eliminateFrameIndex()
1364 : AMDGPU::BUFFER_STORE_DWORD_OFFSET; in eliminateFrameIndex()
1369 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
1376 case AMDGPU::SI_SPILL_V32_RESTORE: in eliminateFrameIndex()
1377 case AMDGPU::SI_SPILL_V64_RESTORE: in eliminateFrameIndex()
1378 case AMDGPU::SI_SPILL_V96_RESTORE: in eliminateFrameIndex()
1379 case AMDGPU::SI_SPILL_V128_RESTORE: in eliminateFrameIndex()
1380 case AMDGPU::SI_SPILL_V160_RESTORE: in eliminateFrameIndex()
1381 case AMDGPU::SI_SPILL_V256_RESTORE: in eliminateFrameIndex()
1382 case AMDGPU::SI_SPILL_V512_RESTORE: in eliminateFrameIndex()
1383 case AMDGPU::SI_SPILL_V1024_RESTORE: in eliminateFrameIndex()
1384 case AMDGPU::SI_SPILL_A32_RESTORE: in eliminateFrameIndex()
1385 case AMDGPU::SI_SPILL_A64_RESTORE: in eliminateFrameIndex()
1386 case AMDGPU::SI_SPILL_A96_RESTORE: in eliminateFrameIndex()
1387 case AMDGPU::SI_SPILL_A128_RESTORE: in eliminateFrameIndex()
1388 case AMDGPU::SI_SPILL_A160_RESTORE: in eliminateFrameIndex()
1389 case AMDGPU::SI_SPILL_A192_RESTORE: in eliminateFrameIndex()
1390 case AMDGPU::SI_SPILL_A256_RESTORE: in eliminateFrameIndex()
1391 case AMDGPU::SI_SPILL_A512_RESTORE: in eliminateFrameIndex()
1392 case AMDGPU::SI_SPILL_A1024_RESTORE: { in eliminateFrameIndex()
1394 AMDGPU::OpName::vdata); in eliminateFrameIndex()
1395 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1398 unsigned Opc = ST.enableFlatScratch() ? AMDGPU::SCRATCH_LOAD_DWORD_SADDR in eliminateFrameIndex()
1399 : AMDGPU::BUFFER_LOAD_DWORD_OFFSET; in eliminateFrameIndex()
1404 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
1425 TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in eliminateFrameIndex()
1435 assert(!TII->getNamedOperand(*MI, AMDGPU::OpName::vaddr) && in eliminateFrameIndex()
1442 unsigned NewOpc = AMDGPU::getFlatScratchInstSTfromSS(Opc); in eliminateFrameIndex()
1444 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr)); in eliminateFrameIndex()
1458 FIOp.ChangeToRegister(AMDGPU::M0, false); in eliminateFrameIndex()
1466 const TargetRegisterClass *RC = UseSGPR ? &AMDGPU::SReg_32_XM0RegClass in eliminateFrameIndex()
1467 : &AMDGPU::VGPR_32RegClass; in eliminateFrameIndex()
1474 unsigned Opc = UseSGPR ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
1486 : RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, in eliminateFrameIndex()
1501 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), TmpSReg) in eliminateFrameIndex()
1506 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1511 BuildMI(*MBB, std::next(MI), DL, TII->get(AMDGPU::S_SUB_U32), in eliminateFrameIndex()
1527 bool IsCopy = MI->getOpcode() == AMDGPU::V_MOV_B32_e32; in eliminateFrameIndex()
1530 : RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
1535 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg) in eliminateFrameIndex()
1543 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), in eliminateFrameIndex()
1548 const bool IsVOP2 = MIB->getOpcode() == AMDGPU::V_ADD_U32_e32; in eliminateFrameIndex()
1551 if (IsVOP2 || AMDGPU::isInlinableLiteral32(Offset, ST.hasInv2PiInlineImm())) { in eliminateFrameIndex()
1558 assert(MIB->getOpcode() == AMDGPU::V_ADD_CO_U32_e64 && in eliminateFrameIndex()
1564 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0); in eliminateFrameIndex()
1568 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg) in eliminateFrameIndex()
1582 RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false); in eliminateFrameIndex()
1585 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg) in eliminateFrameIndex()
1588 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), ScaledReg) in eliminateFrameIndex()
1591 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg) in eliminateFrameIndex()
1596 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScaledReg) in eliminateFrameIndex()
1599 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg) in eliminateFrameIndex()
1617 AMDGPU::getNamedOperandIdx(MI->getOpcode(), in eliminateFrameIndex()
1618 AMDGPU::OpName::vaddr)); in eliminateFrameIndex()
1620 auto &SOffset = *TII->getNamedOperand(*MI, AMDGPU::OpName::soffset); in eliminateFrameIndex()
1625 if (FrameReg == AMDGPU::NoRegister) { in eliminateFrameIndex()
1630 } else if (SOffset.isImm() && FrameReg != AMDGPU::NoRegister) { in eliminateFrameIndex()
1636 = TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(); in eliminateFrameIndex()
1651 Register TmpReg = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0); in eliminateFrameIndex()
1652 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1667 return &AMDGPU::VReg_1RegClass; in getVGPRClassForBitWidth()
1669 return &AMDGPU::VGPR_LO16RegClass; in getVGPRClassForBitWidth()
1671 return &AMDGPU::VGPR_32RegClass; in getVGPRClassForBitWidth()
1673 return &AMDGPU::VReg_64RegClass; in getVGPRClassForBitWidth()
1675 return &AMDGPU::VReg_96RegClass; in getVGPRClassForBitWidth()
1677 return &AMDGPU::VReg_128RegClass; in getVGPRClassForBitWidth()
1679 return &AMDGPU::VReg_160RegClass; in getVGPRClassForBitWidth()
1681 return &AMDGPU::VReg_192RegClass; in getVGPRClassForBitWidth()
1683 return &AMDGPU::VReg_256RegClass; in getVGPRClassForBitWidth()
1685 return &AMDGPU::VReg_512RegClass; in getVGPRClassForBitWidth()
1687 return &AMDGPU::VReg_1024RegClass; in getVGPRClassForBitWidth()
1695 return &AMDGPU::AGPR_LO16RegClass; in getAGPRClassForBitWidth()
1697 return &AMDGPU::AGPR_32RegClass; in getAGPRClassForBitWidth()
1699 return &AMDGPU::AReg_64RegClass; in getAGPRClassForBitWidth()
1701 return &AMDGPU::AReg_96RegClass; in getAGPRClassForBitWidth()
1703 return &AMDGPU::AReg_128RegClass; in getAGPRClassForBitWidth()
1705 return &AMDGPU::AReg_160RegClass; in getAGPRClassForBitWidth()
1707 return &AMDGPU::AReg_192RegClass; in getAGPRClassForBitWidth()
1709 return &AMDGPU::AReg_256RegClass; in getAGPRClassForBitWidth()
1711 return &AMDGPU::AReg_512RegClass; in getAGPRClassForBitWidth()
1713 return &AMDGPU::AReg_1024RegClass; in getAGPRClassForBitWidth()
1721 return &AMDGPU::SGPR_LO16RegClass; in getSGPRClassForBitWidth()
1723 return &AMDGPU::SReg_32RegClass; in getSGPRClassForBitWidth()
1725 return &AMDGPU::SReg_64RegClass; in getSGPRClassForBitWidth()
1727 return &AMDGPU::SGPR_96RegClass; in getSGPRClassForBitWidth()
1729 return &AMDGPU::SGPR_128RegClass; in getSGPRClassForBitWidth()
1731 return &AMDGPU::SGPR_160RegClass; in getSGPRClassForBitWidth()
1733 return &AMDGPU::SGPR_192RegClass; in getSGPRClassForBitWidth()
1735 return &AMDGPU::SGPR_256RegClass; in getSGPRClassForBitWidth()
1737 return &AMDGPU::SGPR_512RegClass; in getSGPRClassForBitWidth()
1739 return &AMDGPU::SGPR_1024RegClass; in getSGPRClassForBitWidth()
1749 &AMDGPU::VGPR_LO16RegClass, in getPhysRegClass()
1750 &AMDGPU::VGPR_HI16RegClass, in getPhysRegClass()
1751 &AMDGPU::SReg_LO16RegClass, in getPhysRegClass()
1752 &AMDGPU::AGPR_LO16RegClass, in getPhysRegClass()
1753 &AMDGPU::VGPR_32RegClass, in getPhysRegClass()
1754 &AMDGPU::SReg_32RegClass, in getPhysRegClass()
1755 &AMDGPU::AGPR_32RegClass, in getPhysRegClass()
1756 &AMDGPU::VReg_64RegClass, in getPhysRegClass()
1757 &AMDGPU::SReg_64RegClass, in getPhysRegClass()
1758 &AMDGPU::AReg_64RegClass, in getPhysRegClass()
1759 &AMDGPU::VReg_96RegClass, in getPhysRegClass()
1760 &AMDGPU::SReg_96RegClass, in getPhysRegClass()
1761 &AMDGPU::AReg_96RegClass, in getPhysRegClass()
1762 &AMDGPU::VReg_128RegClass, in getPhysRegClass()
1763 &AMDGPU::SReg_128RegClass, in getPhysRegClass()
1764 &AMDGPU::AReg_128RegClass, in getPhysRegClass()
1765 &AMDGPU::VReg_160RegClass, in getPhysRegClass()
1766 &AMDGPU::SReg_160RegClass, in getPhysRegClass()
1767 &AMDGPU::AReg_160RegClass, in getPhysRegClass()
1768 &AMDGPU::VReg_192RegClass, in getPhysRegClass()
1769 &AMDGPU::SReg_192RegClass, in getPhysRegClass()
1770 &AMDGPU::AReg_192RegClass, in getPhysRegClass()
1771 &AMDGPU::VReg_256RegClass, in getPhysRegClass()
1772 &AMDGPU::SReg_256RegClass, in getPhysRegClass()
1773 &AMDGPU::AReg_256RegClass, in getPhysRegClass()
1774 &AMDGPU::VReg_512RegClass, in getPhysRegClass()
1775 &AMDGPU::SReg_512RegClass, in getPhysRegClass()
1776 &AMDGPU::AReg_512RegClass, in getPhysRegClass()
1777 &AMDGPU::SReg_1024RegClass, in getPhysRegClass()
1778 &AMDGPU::VReg_1024RegClass, in getPhysRegClass()
1779 &AMDGPU::AReg_1024RegClass, in getPhysRegClass()
1780 &AMDGPU::SCC_CLASSRegClass, in getPhysRegClass()
1781 &AMDGPU::Pseudo_SReg_32RegClass, in getPhysRegClass()
1782 &AMDGPU::Pseudo_SReg_128RegClass, in getPhysRegClass()
1798 return getCommonSubClass(&AMDGPU::VGPR_LO16RegClass, RC) != nullptr || in hasVGPRs()
1799 getCommonSubClass(&AMDGPU::VGPR_HI16RegClass, RC) != nullptr; in hasVGPRs()
1841 return &AMDGPU::SGPR_32RegClass; in getEquivalentSGPRClass()
1849 if (SubIdx == AMDGPU::NoSubRegister) in getSubRegClass()
1856 RC = &AMDGPU::SGPR_32RegClass; in getSubRegClass()
1869 if (OpType >= AMDGPU::OPERAND_REG_INLINE_AC_FIRST && in opCanUseInlineConstant()
1870 OpType <= AMDGPU::OPERAND_REG_INLINE_AC_LAST) in opCanUseInlineConstant()
1873 return OpType >= AMDGPU::OPERAND_SRC_FIRST && in opCanUseInlineConstant()
1874 OpType <= AMDGPU::OPERAND_SRC_LAST; in opCanUseInlineConstant()
1923 const unsigned RegBitWidth = AMDGPU::getRegBitWidth(*RC->MC); in getRegSplitParts()
1987 case AMDGPU::VGPR_32RegClassID: in getRegPressureLimit()
1988 case AMDGPU::VGPR_LO16RegClassID: in getRegPressureLimit()
1989 case AMDGPU::VGPR_HI16RegClassID: in getRegPressureLimit()
1991 case AMDGPU::SGPR_32RegClassID: in getRegPressureLimit()
1992 case AMDGPU::SGPR_LO16RegClassID: in getRegPressureLimit()
1999 if (Idx == AMDGPU::RegisterPressureSets::VGPR_32 || in getRegPressureSetLimit()
2000 Idx == AMDGPU::RegisterPressureSets::AGPR_32) in getRegPressureSetLimit()
2001 return getRegPressureLimit(&AMDGPU::VGPR_32RegClass, in getRegPressureSetLimit()
2004 if (Idx == AMDGPU::RegisterPressureSets::SReg_32) in getRegPressureSetLimit()
2005 return getRegPressureLimit(&AMDGPU::SGPR_32RegClass, in getRegPressureSetLimit()
2022 return AMDGPU::SGPR30_SGPR31; in getReturnAddressReg()
2030 case AMDGPU::VGPRRegBankID: in getRegClassForSizeOnBank()
2032 case AMDGPU::VCCRegBankID: in getRegClassForSizeOnBank()
2034 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
2035 : &AMDGPU::SReg_64_XEXECRegClass; in getRegClassForSizeOnBank()
2036 case AMDGPU::SGPRRegBankID: in getRegClassForSizeOnBank()
2038 case AMDGPU::AGPRRegBankID: in getRegClassForSizeOnBank()
2057 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
2063 case AMDGPU::SReg_1RegClassID: in getRegClass()
2065 case AMDGPU::SReg_1_XEXECRegClassID: in getRegClass()
2066 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
2067 : &AMDGPU::SReg_64_XEXECRegClass; in getRegClass()
2133 for (const TargetRegisterClass &RC : { AMDGPU::VGPR_32RegClass, in get32BitRegister()
2134 AMDGPU::SReg_32RegClass, in get32BitRegister()
2135 AMDGPU::AGPR_32RegClass } ) { in get32BitRegister()
2136 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::lo16, &RC)) in get32BitRegister()
2139 if (MCPhysReg Super = getMatchingSuperReg(Reg, AMDGPU::hi16, in get32BitRegister()
2140 &AMDGPU::VGPR_32RegClass)) { in get32BitRegister()
2144 return AMDGPU::NoRegister; in get32BitRegister()
2149 case AMDGPU::SGPR_NULL: in isConstantPhysReg()
2150 case AMDGPU::SRC_SHARED_BASE: in isConstantPhysReg()
2151 case AMDGPU::SRC_PRIVATE_BASE: in isConstantPhysReg()
2152 case AMDGPU::SRC_SHARED_LIMIT: in isConstantPhysReg()
2153 case AMDGPU::SRC_PRIVATE_LIMIT: in isConstantPhysReg()
2162 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(), in getAllSGPR128()
2168 return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(), in getAllSGPR64()
2174 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); in getAllSGPR32()