954   Register SuperReg = MI->getOperand(0).getReg();  in buildSGPRSpillLoadStore()  local
955   const TargetRegisterClass *RC = getPhysRegClass(SuperReg);  in buildSGPRSpillLoadStore()
965   assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&  in buildSGPRSpillLoadStore()
966          SuperReg != AMDGPU::EXEC && "exec should never spill");  in buildSGPRSpillLoadStore()
970   bool OnlyExecLo = isWave32 || NumSubRegs == 1 || SuperReg == AMDGPU::EXEC_HI;  in buildSGPRSpillLoadStore()
980             ? SuperReg  in buildSGPRSpillLoadStore()
981             : Register(getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]));  in buildSGPRSpillLoadStore()
986           getSubReg(SuperReg, SplitParts[FirstPart + ExecLane]), AMDGPU::sub0,  in buildSGPRSpillLoadStore()
1043               getSubReg(SuperReg, SplitParts[FirstPart + ExecLane + 1]))  in buildSGPRSpillLoadStore()
1050                                   SuperReg, SplitParts[FirstPart + ExecLane])))  in buildSGPRSpillLoadStore()
1073   Register SuperReg = MI->getOperand(0).getReg();  in spillSGPR()  local
1077   assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() &&  in spillSGPR()
1078                          SuperReg != MFI->getFrameOffsetReg()));  in spillSGPR()
1080   assert(SuperReg != AMDGPU::M0 && "m0 should never spill");  in spillSGPR()
1081   assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&  in spillSGPR()
1082          SuperReg != AMDGPU::EXEC && "exec should never spill");  in spillSGPR()
1085   const TargetRegisterClass *RC = getPhysRegClass(SuperReg);  in spillSGPR()
1093                             ? SuperReg  in spillSGPR()
1094                             : Register(getSubReg(SuperReg, SplitParts[i]));  in spillSGPR()
1117         MIB.addReg(SuperReg, RegState::ImplicitDefine);  in spillSGPR()
1121         MIB.addReg(SuperReg, getKillRegState(UseKill) | RegState::Implicit);  in spillSGPR()
1148                               ? SuperReg  in spillSGPR()
1149                               : Register(getSubReg(SuperReg, SplitParts[i]));  in spillSGPR()
1165           WriteLane.addReg(SuperReg, RegState::Implicit | SuperKillState);  in spillSGPR()
1197   Register SuperReg = MI->getOperand(0).getReg();  in restoreSGPR()  local
1199   assert(SuperReg != AMDGPU::M0 && "m0 should never spill");  in restoreSGPR()
1200   assert(SuperReg != AMDGPU::EXEC_LO && SuperReg != AMDGPU::EXEC_HI &&  in restoreSGPR()
1201          SuperReg != AMDGPU::EXEC && "exec should never spill");  in restoreSGPR()
1205   const TargetRegisterClass *RC = getPhysRegClass(SuperReg);  in restoreSGPR()
1213                             ? SuperReg  in restoreSGPR()
1214                             : Register(getSubReg(SuperReg, SplitParts[i]));  in restoreSGPR()
1221         MIB.addReg(SuperReg, RegState::ImplicitDefine);  in restoreSGPR()
1241                               ? SuperReg  in restoreSGPR()
1242                               : Register(getSubReg(SuperReg, SplitParts[i]));  in restoreSGPR()
1250           MIB.addReg(SuperReg, RegState::ImplicitDefine);  in restoreSGPR()