Lines Matching +full:6 +full:u7
24 def immU6 : immU<6>;
31 // e.g. s3 field may encode the signed integers values -1 .. 6
139 // [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
148 // C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
149 // or a 6-bit unsigned immediate (immU6), depending on the format.
171 let Inst{15-6} = S21{20-11};
180 let Inst{15-6} = S25{20-11};
191 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
199 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
207 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
217 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
224 bits<6> B;
225 bits<6> C;
235 let Inst{11-6} = C;
245 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
247 class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
251 bits<6> C;
252 bits<6> B;
260 let Inst{11-6} = C;
268 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
270 class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
273 bits<6> C;
274 bits<6> B;
275 bits<6> A;
283 let Inst{11-6} = C;
289 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
291 class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
295 bits<6> C;
296 bits<6> B;
304 let Inst{11-6} = C;
310 // 2-register, unsigned 6-bit immediate Dual Operand instruction.
311 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
313 class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
316 bits<6> U6;
317 bits<6> B;
318 bits<6> A;
326 let Inst{11-6} = U6;
332 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
333 // |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
334 class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
337 bits<6> B;
346 let Inst{11-6} = S12{5-0};
347 let Inst{5-0} = S12{11-6};
353 class F32_DOP_RLIMM<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
356 bits<6> B;
357 bits<6> A;
367 let Inst{11-6} = 0b111110;
388 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
393 bits<6> B;
394 bits<6> A;
405 let Inst{6} = x;
424 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
429 bits<6> LImmReg = 0b111110;
430 bits<6> A;
441 let Inst{6} = x;
449 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
454 bits<6> LImmReg = 0b111110;
456 bits<6> B;
457 bits<6> A;
471 let Inst{11-6} = LImmReg;
479 // |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
484 bits<6> B;
485 bits<6> C;
493 let Inst{11-6} = C;
514 // |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
519 bits<6> LImmReg = 0b111110;
520 bits<6> C;
528 let Inst{11-6} = C;
539 // |10|9|8|7|6|5|4|3|2|1|0|
576 F16_LD_ADD_SUB<(outs GPR32:$r), (ins GPR32:$b, immU<6>:$u6),
580 bits<6> u6;
583 let Inst{6-4} = u6{5-3};
608 F16_LD_ST_1<(outs GPR32:$b), (ins immU<7>:$u7),
609 "ldi_s\t$b, [$u7]"> {
612 bits<7> u7;
615 let Inst{7-4} = u7{6-3};
617 let Inst{2-0} = u7{2-0};
657 // |10|9|8|7|6|5|4|3|2|1|0|
675 // |10|9|8|7|6|5|4|3|2|1|0|
703 let Size = 6;
760 let Inst{4-0} = off{6-2};
767 bits<6> off;
780 // |10|9|8|7|6|5|4|3|2|1|0|
798 // |10|9|8|7|6|5|4|3|2|1|0|
818 bits<7> u7;
821 let fieldU = u7{6-2};
822 let u7{1-0} = 0b00;
827 (outs), (ins immU<7>:$u7),
828 !strconcat(asmop, "\t%sp, %sp, $u7")> {
850 (outs GPR32Reduced:$b3), (ins immU<7>:$u7),
851 !strconcat(asmop, "\t$b3, [%sp, $u7]")>;
854 (outs), (ins GPR32Reduced:$b3, immU<7>:$u7),
855 !strconcat(asmop, "\t$b3, [%sp, $u7]")>;
867 F16_OP_IMM<0b11100, (outs GPR32:$b), (ins immU<7>:$u7), asmstr> {
869 bits<7> u7;
871 let Inst{6-0} = u7;
925 let Inst{6-0} = s8{7-1};
951 let Inst{8-6} = i;
952 let Inst{5-0} = s{6-1};