47     : ARCGenInstrInfo(ARC::ADJCALLSTACKDOWN, ARC::ADJCALLSTACKUP), RI() {}  in ARCInstrInfo()
54   return Opcode == ARC::LD_rs9 || Opcode == ARC::LDH_rs9 ||  in isLoad()
55          Opcode == ARC::LDB_rs9;  in isLoad()
59   return Opcode == ARC::ST_rs9 || Opcode == ARC::STH_rs9 ||  in isStore()
60          Opcode == ARC::STB_rs9;  in isStore()
137 static bool isUncondBranchOpcode(int Opc) { return Opc == ARC::BR; }  in isUncondBranchOpcode()
140   return Opc == ARC::BRcc_rr_p || Opc == ARC::BRcc_ru6_p;  in isCondBranchOpcode()
143 static bool isJumpOpcode(int Opc) { return Opc == ARC::J; }  in isJumpOpcode()
285   assert(ARC::GPR32RegClass.contains(SrcReg) &&  in copyPhysReg()
287   assert(ARC::GPR32RegClass.contains(DestReg) &&  in copyPhysReg()
289   BuildMI(MBB, I, dl, get(ARC::MOV_rr), DestReg)  in copyPhysReg()
311   assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&  in storeRegToStackSlot()
315   BuildMI(MBB, I, dl, get(ARC::ST_rs9))  in storeRegToStackSlot()
338   assert(ARC::GPR32RegClass.hasSubClassEq(RC) &&  in loadRegFromStackSlot()
342   BuildMI(MBB, I, dl, get(ARC::LD_rs9))  in loadRegFromStackSlot()
363     return BuildMI(MBB, MI, dl, get(ARC::MOV_rs12), Reg)  in loadImmediate()
383     BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB);  in insertBranch()
386   int BccOpc = Cond[1].isImm() ? ARC::BRcc_ru6_p : ARC::BRcc_rr_p;  in insertBranch()
399   BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB);  in insertBranch()