Lines Matching +full:6 +full:u7

120 multiclass ArcBinaryInst<bits<5> major, bits<6> mincode,
133   // 2 register with unsigned 6-bit immediate variant.
174 multiclass ArcSpecialDOPInst<bits<6> subop, string opasm, bit F> {
190 multiclass ArcUnaryInst<bits<5> major, bits<6> subop,
201 multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm> :
203 multiclass ArcBinaryEXT5Inst<bits<6> mincode, string opasm> :
206 multiclass ArcUnaryGEN4Inst<bits<6> mincode, string opasm> :
421                 (outs GPR32Reduced:$b3), (ins immU<7>:$u7),
422                 "add_s\t$b3, %sp, $u7">;
430   (outs), (ins immU<7>:$u7), "leave_s\t$u7"> {
432   bits<7> u7;
434   let fieldB = u7{6-4};
435   let fieldU{4-1} = u7{3-0};
440   (outs), (ins immU<6>:$u6), "enter_s\t$u6"> {
442   bits<6> u6;
467   let Size = 6;
681   F16_OP_U7<0b0, !strconcat("add_s", "\t$b, $b, $u7")>;
684   F16_OP_U7<0b1, !strconcat("cmp_s", "\t$b, $u7")>;
698   F16_LD_ST_HALF_OFF<opc, (outs GPR32:$c), (ins GPR32:$b, immU<6>:$off),
713   F16_LD_ST_HALF_OFF<0x16, (outs), (ins GPR32:$c, GPR32:$b, immU<6>:$off),
747   bits<6> u6;