3377 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,  in getNumMicroOpsSwiftLdSt()  argument
3382     int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());  in getNumMicroOpsSwiftLdSt()
3679 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,  in getNumMicroOps()  argument
3681   if (!ItinData || ItinData->isEmpty())  in getNumMicroOps()
3686   int ItinUOps = ItinData->getNumMicroOps(Class);  in getNumMicroOps()
3689       return getNumMicroOpsSwiftLdSt(ItinData, MI);  in getNumMicroOps()
3793 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,  in getVLDMDefCycle()  argument
3800     return ItinData->getOperandCycle(DefClass, DefIdx);  in getVLDMDefCycle()
3834 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,  in getLDMDefCycle()  argument
3841     return ItinData->getOperandCycle(DefClass, DefIdx);  in getLDMDefCycle()
3869 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,  in getVSTMUseCycle()  argument
3875     return ItinData->getOperandCycle(UseClass, UseIdx);  in getVSTMUseCycle()
3909 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,  in getSTMUseCycle()  argument
3915     return ItinData->getOperandCycle(UseClass, UseIdx);  in getSTMUseCycle()
3938 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
3947     return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);  in getOperandLatency()
3956     DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in getOperandLatency()
3965     DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
3986     DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);  in getOperandLatency()
3997     UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);  in getOperandLatency()
4006     UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
4024     UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);  in getOperandLatency()
4037       if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,  in getOperandLatency()
4040     } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,  in getOperandLatency()
4282 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
4288   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
4314       ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,  in getOperandLatency()
4319     const InstrItineraryData *ItinData, const MachineInstr &DefMI,  in getOperandLatencyImpl()  argument
4334     unsigned Latency = getInstrLatency(ItinData, DefMI);  in getOperandLatencyImpl()
4360   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,  in getOperandLatencyImpl()
4379 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,  in getOperandLatency()  argument
4390   if (!ItinData || ItinData->isEmpty())  in getOperandLatency()
4394     int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);  in getOperandLatency()
4409   int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,  in getOperandLatency()
4656 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4671         Latency += getInstrLatency(ItinData, *I, PredCost);  in getInstrLatency()
4685   if (!ItinData)  in getInstrLatency()
4691   if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)  in getInstrLatency()
4692     return getNumMicroOps(ItinData, MI);  in getInstrLatency()
4695   unsigned Latency = ItinData->getStageLatency(Class);  in getInstrLatency()
4707 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,  in getInstrLatency()  argument
4712   if (!ItinData || ItinData->isEmpty())  in getInstrLatency()
4718     return ItinData->getStageLatency(get(Opcode).getSchedClass());  in getInstrLatency()
4749   const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();  in hasLowDefLatency()  local
4750   if (!ItinData || ItinData->isEmpty())  in hasLowDefLatency()
4756     int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);  in hasLowDefLatency()