Lines Matching full:arm
16 #include "ARM.h"
30 #define DEBUG_TYPE "arm-pseudo"
33 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
34 cl::desc("Verify machine code after expanding ARM pseudos"));
36 #define ARM_EXPAND_PSEUDO_NAME "ARM pseudo instruction expansion pass"
185 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
186 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
187 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
188 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
189 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
190 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
192 { ARM::VLD1d16QPseudo, ARM::VLD1d16Q, true, false, false, SingleSpc, 4, 4 ,false},
193 { ARM::VLD1d16TPseudo, ARM::VLD1d16T, true, false, false, SingleSpc, 3, 4 ,false},
194 { ARM::VLD1d32QPseudo, ARM::VLD1d32Q, true, false, false, SingleSpc, 4, 2 ,false},
195 { ARM::VLD1d32TPseudo, ARM::VLD1d32T, true, false, false, SingleSpc, 3, 2 ,false},
196 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
197 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,fals…
198 { ARM::VLD1d64QPseudoWB_register, ARM::VLD1d64Qwb_register, true, true, true, SingleSpc, 4, 1 …
199 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
200 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,fals…
201 { ARM::VLD1d64TPseudoWB_register, ARM::VLD1d64Twb_register, true, true, true, SingleSpc, 3, 1 ,f…
202 { ARM::VLD1d8QPseudo, ARM::VLD1d8Q, true, false, false, SingleSpc, 4, 8 ,false},
203 { ARM::VLD1d8TPseudo, ARM::VLD1d8T, true, false, false, SingleSpc, 3, 8 ,false},
204 { ARM::VLD1q16HighQPseudo, ARM::VLD1d16Q, true, false, false, SingleHighQSpc, 4, 4 ,false},
205 { ARM::VLD1q16HighTPseudo, ARM::VLD1d16T, true, false, false, SingleHighTSpc, 3, 4 ,false},
206 { ARM::VLD1q16LowQPseudo_UPD, ARM::VLD1d16Qwb_fixed, true, true, true, SingleLowSpc, 4, 4 ,fal…
207 { ARM::VLD1q16LowTPseudo_UPD, ARM::VLD1d16Twb_fixed, true, true, true, SingleLowSpc, 3, 4 ,fal…
208 { ARM::VLD1q32HighQPseudo, ARM::VLD1d32Q, true, false, false, SingleHighQSpc, 4, 2 ,false},
209 { ARM::VLD1q32HighTPseudo, ARM::VLD1d32T, true, false, false, SingleHighTSpc, 3, 2 ,false},
210 { ARM::VLD1q32LowQPseudo_UPD, ARM::VLD1d32Qwb_fixed, true, true, true, SingleLowSpc, 4, 2 ,fal…
211 { ARM::VLD1q32LowTPseudo_UPD, ARM::VLD1d32Twb_fixed, true, true, true, SingleLowSpc, 3, 2 ,fal…
212 { ARM::VLD1q64HighQPseudo, ARM::VLD1d64Q, true, false, false, SingleHighQSpc, 4, 1 ,false},
213 { ARM::VLD1q64HighTPseudo, ARM::VLD1d64T, true, false, false, SingleHighTSpc, 3, 1 ,false},
214 { ARM::VLD1q64LowQPseudo_UPD, ARM::VLD1d64Qwb_fixed, true, true, true, SingleLowSpc, 4, 1 ,fal…
215 { ARM::VLD1q64LowTPseudo_UPD, ARM::VLD1d64Twb_fixed, true, true, true, SingleLowSpc, 3, 1 ,fal…
216 { ARM::VLD1q8HighQPseudo, ARM::VLD1d8Q, true, false, false, SingleHighQSpc, 4, 8 ,false},
217 { ARM::VLD1q8HighTPseudo, ARM::VLD1d8T, true, false, false, SingleHighTSpc, 3, 8 ,false},
218 { ARM::VLD1q8LowQPseudo_UPD, ARM::VLD1d8Qwb_fixed, true, true, true, SingleLowSpc, 4, 8 ,false…
219 { ARM::VLD1q8LowTPseudo_UPD, ARM::VLD1d8Twb_fixed, true, true, true, SingleLowSpc, 3, 8 ,false…
221 { ARM::VLD2DUPq16EvenPseudo, ARM::VLD2DUPd16x2, true, false, false, EvenDblSpc, 2, 4 ,false},
222 { ARM::VLD2DUPq16OddPseudo, ARM::VLD2DUPd16x2, true, false, false, OddDblSpc, 2, 4 ,false},
223 { ARM::VLD2DUPq32EvenPseudo, ARM::VLD2DUPd32x2, true, false, false, EvenDblSpc, 2, 2 ,false},
224 { ARM::VLD2DUPq32OddPseudo, ARM::VLD2DUPd32x2, true, false, false, OddDblSpc, 2, 2 ,false},
225 { ARM::VLD2DUPq8EvenPseudo, ARM::VLD2DUPd8x2, true, false, false, EvenDblSpc, 2, 8 ,false},
226 { ARM::VLD2DUPq8OddPseudo, ARM::VLD2DUPd8x2, true, false, false, OddDblSpc, 2, 8 ,false},
228 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
229 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
230 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
231 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
232 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
233 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
234 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
235 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
236 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
237 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
239 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
240 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
241 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,fa…
242 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
243 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
244 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,fa…
245 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
246 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
247 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,fal…
249 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
250 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
251 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
252 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
253 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
254 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
255 { ARM::VLD3DUPq16EvenPseudo, ARM::VLD3DUPq16, true, false, false, EvenDblSpc, 3, 4 ,true},
256 { ARM::VLD3DUPq16OddPseudo, ARM::VLD3DUPq16, true, false, false, OddDblSpc, 3, 4 ,true},
257 { ARM::VLD3DUPq32EvenPseudo, ARM::VLD3DUPq32, true, false, false, EvenDblSpc, 3, 2 ,true},
258 { ARM::VLD3DUPq32OddPseudo, ARM::VLD3DUPq32, true, false, false, OddDblSpc, 3, 2 ,true},
259 { ARM::VLD3DUPq8EvenPseudo, ARM::VLD3DUPq8, true, false, false, EvenDblSpc, 3, 8 ,true},
260 { ARM::VLD3DUPq8OddPseudo, ARM::VLD3DUPq8, true, false, false, OddDblSpc, 3, 8 ,true},
262 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
263 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
264 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
265 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
266 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
267 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
268 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
269 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
270 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
271 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
273 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
274 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
275 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
276 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
277 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
278 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
280 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
281 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
282 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
283 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
284 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
285 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
286 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
287 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
288 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
290 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
291 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
292 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
293 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
294 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
295 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
296 { ARM::VLD4DUPq16EvenPseudo, ARM::VLD4DUPq16, true, false, false, EvenDblSpc, 4, 4 ,true},
297 { ARM::VLD4DUPq16OddPseudo, ARM::VLD4DUPq16, true, false, false, OddDblSpc, 4, 4 ,true},
298 { ARM::VLD4DUPq32EvenPseudo, ARM::VLD4DUPq32, true, false, false, EvenDblSpc, 4, 2 ,true},
299 { ARM::VLD4DUPq32OddPseudo, ARM::VLD4DUPq32, true, false, false, OddDblSpc, 4, 2 ,true},
300 { ARM::VLD4DUPq8EvenPseudo, ARM::VLD4DUPq8, true, false, false, EvenDblSpc, 4, 8 ,true},
301 { ARM::VLD4DUPq8OddPseudo, ARM::VLD4DUPq8, true, false, false, OddDblSpc, 4, 8 ,true},
303 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
304 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
305 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
306 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
307 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
308 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
309 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
310 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
311 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
312 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
314 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
315 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
316 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
317 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
318 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
319 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
321 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
322 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
323 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
324 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
325 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
326 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
327 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
328 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
329 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
331 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
332 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
333 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
334 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
335 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
336 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
338 { ARM::VST1d16QPseudo, ARM::VST1d16Q, false, false, false, SingleSpc, 4, 4 ,false},
339 { ARM::VST1d16TPseudo, ARM::VST1d16T, false, false, false, SingleSpc, 3, 4 ,false},
340 { ARM::VST1d32QPseudo, ARM::VST1d32Q, false, false, false, SingleSpc, 4, 2 ,false},
341 { ARM::VST1d32TPseudo, ARM::VST1d32T, false, false, false, SingleSpc, 3, 2 ,false},
342 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
343 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false…
344 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,f…
345 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
346 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false…
347 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,…
348 { ARM::VST1d8QPseudo, ARM::VST1d8Q, false, false, false, SingleSpc, 4, 8 ,false},
349 { ARM::VST1d8TPseudo, ARM::VST1d8T, false, false, false, SingleSpc, 3, 8 ,false},
350 { ARM::VST1q16HighQPseudo, ARM::VST1d16Q, false, false, false, SingleHighQSpc, 4, 4 ,false},
351 { ARM::VST1q16HighTPseudo, ARM::VST1d16T, false, false, false, SingleHighTSpc, 3, 4 ,false},
352 { ARM::VST1q16LowQPseudo_UPD, ARM::VST1d16Qwb_fixed, false, true, true, SingleLowSpc, 4, 4 ,fa…
353 { ARM::VST1q16LowTPseudo_UPD, ARM::VST1d16Twb_fixed, false, true, true, SingleLowSpc, 3, 4 ,fa…
354 { ARM::VST1q32HighQPseudo, ARM::VST1d32Q, false, false, false, SingleHighQSpc, 4, 2 ,false},
355 { ARM::VST1q32HighTPseudo, ARM::VST1d32T, false, false, false, SingleHighTSpc, 3, 2 ,false},
356 { ARM::VST1q32LowQPseudo_UPD, ARM::VST1d32Qwb_fixed, false, true, true, SingleLowSpc, 4, 2 ,fa…
357 { ARM::VST1q32LowTPseudo_UPD, ARM::VST1d32Twb_fixed, false, true, true, SingleLowSpc, 3, 2 ,fa…
358 { ARM::VST1q64HighQPseudo, ARM::VST1d64Q, false, false, false, SingleHighQSpc, 4, 1 ,false},
359 { ARM::VST1q64HighTPseudo, ARM::VST1d64T, false, false, false, SingleHighTSpc, 3, 1 ,false},
360 { ARM::VST1q64LowQPseudo_UPD, ARM::VST1d64Qwb_fixed, false, true, true, SingleLowSpc, 4, 1 ,fa…
361 { ARM::VST1q64LowTPseudo_UPD, ARM::VST1d64Twb_fixed, false, true, true, SingleLowSpc, 3, 1 ,fa…
362 { ARM::VST1q8HighQPseudo, ARM::VST1d8Q, false, false, false, SingleHighQSpc, 4, 8 ,false},
363 { ARM::VST1q8HighTPseudo, ARM::VST1d8T, false, false, false, SingleHighTSpc, 3, 8 ,false},
364 { ARM::VST1q8LowQPseudo_UPD, ARM::VST1d8Qwb_fixed, false, true, true, SingleLowSpc, 4, 8 ,fals…
365 { ARM::VST1q8LowTPseudo_UPD, ARM::VST1d8Twb_fixed, false, true, true, SingleLowSpc, 3, 8 ,fals…
367 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
368 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
369 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
370 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
371 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
372 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
373 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
374 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
375 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
376 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
378 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
379 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
380 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,f…
381 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
382 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
383 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,f…
384 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
385 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
386 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,fa…
388 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
389 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
390 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
391 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
392 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
393 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
394 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
395 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
396 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
397 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
399 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
400 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
401 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
402 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
403 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
404 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
406 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
407 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
408 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
409 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
410 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
411 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
412 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
413 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
414 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
416 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
417 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
418 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
419 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
420 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
421 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
422 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
423 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
424 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
425 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
427 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
428 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
429 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
430 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
431 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
432 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
434 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
435 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
436 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
437 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
438 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
439 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
440 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
441 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
442 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
470 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
471 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
472 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
473 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
475 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
476 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
477 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
478 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
480 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
481 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
482 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
483 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
485 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
486 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
487 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
488 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
491 D0 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
492 D1 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
493 D2 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
494 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
516 if(TableEntry->RealOpc == ARM::VLD2DUPd8x2 || in ExpandVLD()
517 TableEntry->RealOpc == ARM::VLD2DUPd16x2 || in ExpandVLD()
518 TableEntry->RealOpc == ARM::VLD2DUPd32x2) { in ExpandVLD()
521 SubRegIndex = ARM::dsub_0; in ExpandVLD()
524 SubRegIndex = ARM::dsub_1; in ExpandVLD()
527 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0, in ExpandVLD()
528 &ARM::DPairSpcRegClass); in ExpandVLD()
559 if (TableEntry->RealOpc == ARM::VLD1d8Qwb_fixed || in ExpandVLD()
560 TableEntry->RealOpc == ARM::VLD1d16Qwb_fixed || in ExpandVLD()
561 TableEntry->RealOpc == ARM::VLD1d32Qwb_fixed || in ExpandVLD()
562 TableEntry->RealOpc == ARM::VLD1d64Qwb_fixed || in ExpandVLD()
563 TableEntry->RealOpc == ARM::VLD1d8Twb_fixed || in ExpandVLD()
564 TableEntry->RealOpc == ARM::VLD1d16Twb_fixed || in ExpandVLD()
565 TableEntry->RealOpc == ARM::VLD1d32Twb_fixed || in ExpandVLD()
566 TableEntry->RealOpc == ARM::VLD1d64Twb_fixed) { in ExpandVLD()
579 if(TableEntry->RealOpc != ARM::VLD2DUPd8x2 && in ExpandVLD()
580 TableEntry->RealOpc != ARM::VLD2DUPd16x2 && in ExpandVLD()
581 TableEntry->RealOpc != ARM::VLD2DUPd32x2) { in ExpandVLD()
640 if (TableEntry->RealOpc == ARM::VST1d8Qwb_fixed || in ExpandVST()
641 TableEntry->RealOpc == ARM::VST1d16Qwb_fixed || in ExpandVST()
642 TableEntry->RealOpc == ARM::VST1d32Qwb_fixed || in ExpandVST()
643 TableEntry->RealOpc == ARM::VST1d64Qwb_fixed || in ExpandVST()
644 TableEntry->RealOpc == ARM::VST1d8Twb_fixed || in ExpandVST()
645 TableEntry->RealOpc == ARM::VST1d16Twb_fixed || in ExpandVST()
646 TableEntry->RealOpc == ARM::VST1d32Twb_fixed || in ExpandVST()
647 TableEntry->RealOpc == ARM::VST1d64Twb_fixed) { in ExpandVST()
865 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; in ExpandMOV32BitImm()
872 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { in ExpandMOV32BitImm()
873 // FIXME Windows CE supports older ARM CPUs in ExpandMOV32BitImm()
874 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); in ExpandMOV32BitImm()
881 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
882 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
888 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
889 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri)) in ExpandMOV32BitImm()
916 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { in ExpandMOV32BitImm()
917 LO16Opc = ARM::t2MOVi16; in ExpandMOV32BitImm()
918 HI16Opc = ARM::t2MOVTi16; in ExpandMOV32BitImm()
920 LO16Opc = ARM::MOVi16; in ExpandMOV32BitImm()
921 HI16Opc = ARM::MOVTi16; in ExpandMOV32BitImm()
1000 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2CLRM)).add(predOps(ARMCC::AL)); in CMSEClearGPRegs()
1003 CLRM.addReg(ARM::APSR, RegState::Define); in CMSEClearGPRegs()
1004 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1011 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVr), Reg) in CMSEClearGPRegs()
1016 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2MSR_M)) in CMSEClearGPRegs()
1036 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in determineFPRegsToClear()
1037 (Reg >= ARM::D0 && Reg <= ARM::D15) || in determineFPRegsToClear()
1038 (Reg >= ARM::S0 && Reg <= ARM::S31)) in determineFPRegsToClear()
1043 if (Reg >= ARM::Q0 && Reg <= ARM::Q7) { in determineFPRegsToClear()
1044 int R = Reg - ARM::Q0; in determineFPRegsToClear()
1046 } else if (Reg >= ARM::D0 && Reg <= ARM::D15) { in determineFPRegsToClear()
1047 int R = Reg - ARM::D0; in determineFPRegsToClear()
1049 } else if (Reg >= ARM::S0 && Reg <= ARM::S31) { in determineFPRegsToClear()
1050 ClearRegs[Reg - ARM::S0] = false; in determineFPRegsToClear()
1106 if (Reg == ARM::NoRegister || Reg == ARM::LR) in CMSEClearFPRegsV8()
1112 ClearBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1113 DoneBB->addLiveIn(ARM::LR); in CMSEClearFPRegsV8()
1116 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2MRS_M), ARM::R12) in CMSEClearFPRegsV8()
1120 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::t2TSTri)) in CMSEClearFPRegsV8()
1121 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1125 BuildMI(MBB, MBB.end(), DL, TII->get(ARM::tBcc)) in CMSEClearFPRegsV8()
1128 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1135 unsigned Reg = ARM::D0 + D; in CMSEClearFPRegsV8()
1136 BuildMI(ClearBB, DL, TII->get(ARM::VMOVDRR), Reg) in CMSEClearFPRegsV8()
1137 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1138 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1143 unsigned Reg = ARM::S0 + D * 2; in CMSEClearFPRegsV8()
1144 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1145 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1150 unsigned Reg = ARM::S0 + D * 2 + 1; in CMSEClearFPRegsV8()
1151 BuildMI(ClearBB, DL, TII->get(ARM::VMOVSR), Reg) in CMSEClearFPRegsV8()
1152 .addReg(ARM::LR) in CMSEClearFPRegsV8()
1160 BuildMI(ClearBB, DL, TII->get(ARM::VMRS), ARM::R12) in CMSEClearFPRegsV8()
1162 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1163 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1167 BuildMI(ClearBB, DL, TII->get(ARM::t2BICri), ARM::R12) in CMSEClearFPRegsV8()
1168 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1172 BuildMI(ClearBB, DL, TII->get(ARM::VMSR)) in CMSEClearFPRegsV8()
1173 .addReg(ARM::R12) in CMSEClearFPRegsV8()
1196 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1199 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1200 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1207 BuildMI(MBB, MBBI, RetI.getDebugLoc(), TII->get(ARM::VSCCLRMS)) in CMSEClearFPRegsV81()
1210 VSCCLRM.addReg(ARM::S0 + Start, RegState::Define); in CMSEClearFPRegsV81()
1211 VSCCLRM.addReg(ARM::VPR, RegState::Define); in CMSEClearFPRegsV81()
1238 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV8()
1239 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1249 assert(!ARM::DPRRegClass.contains(Reg) || in CMSESaveClearFPRegsV8()
1250 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1251 assert(!ARM::QPRRegClass.contains(Reg)); in CMSESaveClearFPRegsV8()
1252 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1259 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSESaveClearFPRegsV8()
1267 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1273 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSESaveClearFPRegsV8()
1286 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV8()
1287 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1289 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV8()
1290 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV8()
1298 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1299 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSESaveClearFPRegsV8()
1303 else if (ARM::SPRRegClass.contains(Reg)) in CMSESaveClearFPRegsV8()
1304 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSESaveClearFPRegsV8()
1310 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1312 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRD), Reg) in CMSESaveClearFPRegsV8()
1313 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1314 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1319 unsigned SReg0 = TRI->getSubReg(Reg, ARM::ssub_0); in CMSESaveClearFPRegsV8()
1320 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0) in CMSESaveClearFPRegsV8()
1321 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1322 .addImm((Reg - ARM::D0) * 2) in CMSESaveClearFPRegsV8()
1324 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), SReg0 + 1) in CMSESaveClearFPRegsV8()
1325 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1326 .addImm((Reg - ARM::D0) * 2 + 1) in CMSESaveClearFPRegsV8()
1329 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSESaveClearFPRegsV8()
1330 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDRS), Reg) in CMSESaveClearFPRegsV8()
1331 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1332 .addImm(Reg - ARM::S0) in CMSESaveClearFPRegsV8()
1339 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2LDRi8), SpareReg) in CMSESaveClearFPRegsV8()
1340 .addReg(ARM::SP) in CMSESaveClearFPRegsV8()
1343 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1348 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), SpareReg) in CMSESaveClearFPRegsV8()
1353 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMSR)) in CMSESaveClearFPRegsV8()
1374 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBspi), ARM::SP) in CMSESaveClearFPRegsV81()
1375 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1380 MachineInstrBuilder VLSTM = BuildMI(MBB, MBBI, DL, TII->get(ARM::VLSTM)) in CMSESaveClearFPRegsV81()
1381 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1383 for (auto R : {ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV, ARM::Q0, ARM::Q1, in CMSESaveClearFPRegsV81()
1384 ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7}) in CMSESaveClearFPRegsV81()
1390 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTMSDB_UPD), ARM::SP) in CMSESaveClearFPRegsV81()
1391 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1393 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSESaveClearFPRegsV81()
1400 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTR_FPCXTS_pre), ARM::SP) in CMSESaveClearFPRegsV81()
1401 .addReg(ARM::SP) in CMSESaveClearFPRegsV81()
1429 assert(!ARM::DPRRegClass.contains(Reg) || in CMSERestoreFPRegsV8()
1430 ARM::DPR_VFP2RegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1431 assert(!ARM::QPRRegClass.contains(Reg)); in CMSERestoreFPRegsV8()
1432 if (ARM::DPR_VFP2RegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1439 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRRD)) in CMSERestoreFPRegsV8()
1447 } else if (ARM::SPRRegClass.contains(Reg)) { in CMSERestoreFPRegsV8()
1453 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVRS), SaveReg) in CMSERestoreFPRegsV8()
1465 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1466 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRD), Reg) in CMSERestoreFPRegsV8()
1467 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1468 .addImm((Reg - ARM::D0) * 2) in CMSERestoreFPRegsV8()
1470 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1471 BuildMI(MBB, MBBI, DL, TII->get(ARM::VSTRS), Reg) in CMSERestoreFPRegsV8()
1472 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1473 .addImm(Reg - ARM::S0) in CMSERestoreFPRegsV8()
1478 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV8()
1479 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1486 if (ARM::DPR_VFP2RegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1487 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVDRR), Reg) in CMSERestoreFPRegsV8()
1491 else if (ARM::SPRRegClass.contains(Reg)) in CMSERestoreFPRegsV8()
1492 BuildMI(MBB, MBBI, DL, TII->get(ARM::VMOVSR), Reg) in CMSERestoreFPRegsV8()
1498 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV8()
1499 .addReg(ARM::SP) in CMSERestoreFPRegsV8()
1509 if ((Reg >= ARM::Q0 && Reg <= ARM::Q7) || in definesOrUsesFPReg()
1510 (Reg >= ARM::D0 && Reg <= ARM::D15) || in definesOrUsesFPReg()
1511 (Reg >= ARM::S0 && Reg <= ARM::S31)) in definesOrUsesFPReg()
1522 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLLDM)) in CMSERestoreFPRegsV81()
1523 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1527 BuildMI(MBB, MBBI, DL, TII->get(ARM::tADDspi), ARM::SP) in CMSERestoreFPRegsV81()
1528 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1533 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::VLDR_FPCXTS_post), in CMSERestoreFPRegsV81()
1534 ARM::SP) in CMSERestoreFPRegsV81()
1535 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1541 BuildMI(MBB, MBBI, DL, TII->get(ARM::VLDMSIA_UPD), ARM::SP) in CMSERestoreFPRegsV81()
1542 .addReg(ARM::SP) in CMSERestoreFPRegsV81()
1544 for (int Reg = ARM::S16; Reg <= ARM::S31; ++Reg) in CMSERestoreFPRegsV81()
1595 if (LdrexOp == ARM::t2LDREX) in ExpandCMP_SWAP()
1599 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP()
1604 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP()
1608 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1619 if (StrexOp == ARM::t2STREX) in ExpandCMP_SWAP()
1623 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP()
1631 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1657 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
1664 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair()
1665 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1); in addExclusiveRegPair()
1689 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0); in ExpandCMP_SWAP_64()
1690 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1); in ExpandCMP_SWAP_64()
1691 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0); in ExpandCMP_SWAP_64()
1692 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1); in ExpandCMP_SWAP_64()
1708 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD; in ExpandCMP_SWAP_64()
1714 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr; in ExpandCMP_SWAP_64()
1723 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1725 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; in ExpandCMP_SWAP_64()
1729 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1737 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD; in ExpandCMP_SWAP_64()
1743 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri; in ExpandCMP_SWAP_64()
1751 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1784 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in CMSEPushCalleeSaves()
1785 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves()
1797 for (int LoReg = ARM::R7, HiReg = ARM::R11; LoReg >= ARM::R4; --LoReg) { in CMSEPushCalleeSaves()
1800 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1806 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL)); in CMSEPushCalleeSaves()
1807 for (int Reg = ARM::R4; Reg < ARM::R8; ++Reg) { in CMSEPushCalleeSaves()
1816 if (JumpReg >= ARM::R4 && JumpReg <= ARM::R7) { in CMSEPushCalleeSaves()
1817 int LoReg = JumpReg == ARM::R4 ? ARM::R5 : ARM::R4; in CMSEPushCalleeSaves()
1818 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), LoReg) in CMSEPushCalleeSaves()
1819 .addReg(ARM::R8, LiveRegs.contains(ARM::R8) ? 0 : RegState::Undef) in CMSEPushCalleeSaves()
1821 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPUSH)) in CMSEPushCalleeSaves()
1827 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2STMDB_UPD), ARM::SP) in CMSEPushCalleeSaves()
1828 .addReg(ARM::SP) in CMSEPushCalleeSaves()
1830 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) { in CMSEPushCalleeSaves()
1844 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in CMSEPopCalleeSaves()
1846 PopMIB.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
1847 BuildMI(MBB, MBBI, DL, TII.get(ARM::tMOVr), ARM::R8 + R) in CMSEPopCalleeSaves()
1848 .addReg(ARM::R4 + R, RegState::Kill) in CMSEPopCalleeSaves()
1852 BuildMI(MBB, MBBI, DL, TII.get(ARM::tPOP)).add(predOps(ARMCC::AL)); in CMSEPopCalleeSaves()
1854 PopMIB2.addReg(ARM::R4 + R, RegState::Define); in CMSEPopCalleeSaves()
1857 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2LDMIA_UPD), ARM::SP) in CMSEPopCalleeSaves()
1858 .addReg(ARM::SP) in CMSEPopCalleeSaves()
1860 for (int Reg = ARM::R4; Reg < ARM::R12; ++Reg) in CMSEPopCalleeSaves()
1874 case ARM::VBSPd: in ExpandMI()
1875 case ARM::VBSPq: { in ExpandMI()
1879 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBITd : ARM::VBITq; in ExpandMI()
1889 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBIFd : ARM::VBIFq; in ExpandMI()
1899 unsigned NewOpc = Opcode == ARM::VBSPd ? ARM::VBSLd : ARM::VBSLq; in ExpandMI()
1910 unsigned MoveOpc = Opcode == ARM::VBSPd ? ARM::VORRd : ARM::VORRq; in ExpandMI()
1934 case ARM::TCRETURNdi: in ExpandMI()
1935 case ARM::TCRETURNri: { in ExpandMI()
1949 if (RetOpcode == ARM::TCRETURNdi) { in ExpandMI()
1952 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND) in ExpandMI()
1953 : ARM::TAILJMPd; in ExpandMI()
1967 } else if (RetOpcode == ARM::TCRETURNri) { in ExpandMI()
1969 STI->isThumb() ? ARM::tTAILJMPr in ExpandMI()
1970 : (STI->hasV4TOps() ? ARM::TAILJMPr : ARM::TAILJMPr4); in ExpandMI()
1989 case ARM::tBXNS_RET: { in ExpandMI()
1995 TII->get(ARM::VLDR_FPCXTNS_post), ARM::SP) in ExpandMI()
1996 .addReg(ARM::SP) in ExpandMI()
2003 return !Op.isReg() || Op.getReg() != ARM::R12; in ExpandMI()
2007 *MBBI, {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R12}, ClearRegs); in ExpandMI()
2009 ARM::LR); in ExpandMI()
2013 TII->get(ARM::tBXNS)) in ExpandMI()
2014 .addReg(ARM::LR) in ExpandMI()
2021 case ARM::tBLXNS_CALL: { in ExpandMI()
2040 {ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, in ExpandMI()
2041 ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, in ExpandMI()
2042 ARM::R10, ARM::R11, ARM::R12}, in ExpandMI()
2052 BuildMI(MBB, MBBI, DL, TII->get(ARM::t2BICri), JumpReg) in ExpandMI()
2061 BuildMI(MBB, MBBI, DL, TII->get(ARM::tMOVi8), ScratchReg) in ExpandMI()
2065 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBIC), JumpReg) in ExpandMI()
2066 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2077 BuildMI(MBB, MBBI, DL, TII->get(ARM::tBLXNSr)) in ExpandMI()
2093 case ARM::VMOVHcc: in ExpandMI()
2094 case ARM::VMOVScc: in ExpandMI()
2095 case ARM::VMOVDcc: { in ExpandMI()
2096 unsigned newOpc = Opcode != ARM::VMOVDcc ? ARM::VMOVS : ARM::VMOVD; in ExpandMI()
2107 case ARM::t2MOVCCr: in ExpandMI()
2108 case ARM::MOVCCr: { in ExpandMI()
2109 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; in ExpandMI()
2121 case ARM::MOVCCsi: { in ExpandMI()
2122 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2134 case ARM::MOVCCsr: { in ExpandMI()
2135 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), in ExpandMI()
2148 case ARM::t2MOVCCi16: in ExpandMI()
2149 case ARM::MOVCCi16: { in ExpandMI()
2150 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; in ExpandMI()
2160 case ARM::t2MOVCCi: in ExpandMI()
2161 case ARM::MOVCCi: { in ExpandMI()
2162 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; in ExpandMI()
2174 case ARM::t2MVNCCi: in ExpandMI()
2175 case ARM::MVNCCi: { in ExpandMI()
2176 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; in ExpandMI()
2188 case ARM::t2MOVCClsl: in ExpandMI()
2189 case ARM::t2MOVCClsr: in ExpandMI()
2190 case ARM::t2MOVCCasr: in ExpandMI()
2191 case ARM::t2MOVCCror: { in ExpandMI()
2194 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; in ExpandMI()
2195 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; in ExpandMI()
2196 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; in ExpandMI()
2197 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; in ExpandMI()
2211 case ARM::Int_eh_sjlj_dispatchsetup: { in ExpandMI()
2226 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2229 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2232 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, in ExpandMI()
2247 ARM::t2BICri : ARM::BICri; in ExpandMI()
2248 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6) in ExpandMI()
2249 .addReg(ARM::R6, RegState::Kill) in ExpandMI()
2260 case ARM::MOVsrl_flag: in ExpandMI()
2261 case ARM::MOVsra_flag: { in ExpandMI()
2263 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2267 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) in ExpandMI()
2269 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2273 case ARM::RRX: { in ExpandMI()
2276 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), in ExpandMI()
2286 case ARM::tTPsoft: in ExpandMI()
2287 case ARM::TPsoft: { in ExpandMI()
2288 const bool Thumb = Opcode == ARM::tTPsoft; in ExpandMI()
2301 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg) in ExpandMI()
2308 TII->get(Thumb ? ARM::tBLXr : ARM::BLX)); in ExpandMI()
2314 TII->get(Thumb ? ARM::tBL : ARM::BL)); in ExpandMI()
2328 case ARM::tLDRpci_pic: in ExpandMI()
2329 case ARM::t2LDRpci_pic: { in ExpandMI()
2330 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) in ExpandMI()
2331 ? ARM::tLDRpci : ARM::t2LDRpci; in ExpandMI()
2340 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) in ExpandMI()
2349 case ARM::LDRLIT_ga_abs: in ExpandMI()
2350 case ARM::LDRLIT_ga_pcrel: in ExpandMI()
2351 case ARM::LDRLIT_ga_pcrel_ldr: in ExpandMI()
2352 case ARM::tLDRLIT_ga_abs: in ExpandMI()
2353 case ARM::tLDRLIT_ga_pcrel: { in ExpandMI()
2360 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
2362 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; in ExpandMI()
2363 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; in ExpandMI()
2366 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
2367 : ARM::tPICADD; in ExpandMI()
2407 case ARM::MOV_ga_pcrel: in ExpandMI()
2408 case ARM::MOV_ga_pcrel_ldr: in ExpandMI()
2409 case ARM::t2MOV_ga_pcrel: { in ExpandMI()
2417 bool isARM = Opcode != ARM::t2MOV_ga_pcrel; in ExpandMI()
2418 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; in ExpandMI()
2419 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; in ExpandMI()
2423 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) in ExpandMI()
2424 : ARM::tPICADD; in ExpandMI()
2441 if (Opcode == ARM::MOV_ga_pcrel_ldr) in ExpandMI()
2449 case ARM::MOVi32imm: in ExpandMI()
2450 case ARM::MOVCCi32imm: in ExpandMI()
2451 case ARM::t2MOVi32imm: in ExpandMI()
2452 case ARM::t2MOVCCi32imm: in ExpandMI()
2456 case ARM::SUBS_PC_LR: { in ExpandMI()
2458 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) in ExpandMI()
2459 .addReg(ARM::LR) in ExpandMI()
2463 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
2468 case ARM::VLDMQIA: { in ExpandMI()
2469 unsigned NewOpc = ARM::VLDMDIA; in ExpandMI()
2486 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0); in ExpandMI()
2487 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1); in ExpandMI()
2499 case ARM::VSTMQIA: { in ExpandMI()
2500 unsigned NewOpc = ARM::VSTMDIA; in ExpandMI()
2518 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); in ExpandMI()
2519 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); in ExpandMI()
2532 case ARM::VLD2q8Pseudo: in ExpandMI()
2533 case ARM::VLD2q16Pseudo: in ExpandMI()
2534 case ARM::VLD2q32Pseudo: in ExpandMI()
2535 case ARM::VLD2q8PseudoWB_fixed: in ExpandMI()
2536 case ARM::VLD2q16PseudoWB_fixed: in ExpandMI()
2537 case ARM::VLD2q32PseudoWB_fixed: in ExpandMI()
2538 case ARM::VLD2q8PseudoWB_register: in ExpandMI()
2539 case ARM::VLD2q16PseudoWB_register: in ExpandMI()
2540 case ARM::VLD2q32PseudoWB_register: in ExpandMI()
2541 case ARM::VLD3d8Pseudo: in ExpandMI()
2542 case ARM::VLD3d16Pseudo: in ExpandMI()
2543 case ARM::VLD3d32Pseudo: in ExpandMI()
2544 case ARM::VLD1d8TPseudo: in ExpandMI()
2545 case ARM::VLD1d16TPseudo: in ExpandMI()
2546 case ARM::VLD1d32TPseudo: in ExpandMI()
2547 case ARM::VLD1d64TPseudo: in ExpandMI()
2548 case ARM::VLD1d64TPseudoWB_fixed: in ExpandMI()
2549 case ARM::VLD1d64TPseudoWB_register: in ExpandMI()
2550 case ARM::VLD3d8Pseudo_UPD: in ExpandMI()
2551 case ARM::VLD3d16Pseudo_UPD: in ExpandMI()
2552 case ARM::VLD3d32Pseudo_UPD: in ExpandMI()
2553 case ARM::VLD3q8Pseudo_UPD: in ExpandMI()
2554 case ARM::VLD3q16Pseudo_UPD: in ExpandMI()
2555 case ARM::VLD3q32Pseudo_UPD: in ExpandMI()
2556 case ARM::VLD3q8oddPseudo: in ExpandMI()
2557 case ARM::VLD3q16oddPseudo: in ExpandMI()
2558 case ARM::VLD3q32oddPseudo: in ExpandMI()
2559 case ARM::VLD3q8oddPseudo_UPD: in ExpandMI()
2560 case ARM::VLD3q16oddPseudo_UPD: in ExpandMI()
2561 case ARM::VLD3q32oddPseudo_UPD: in ExpandMI()
2562 case ARM::VLD4d8Pseudo: in ExpandMI()
2563 case ARM::VLD4d16Pseudo: in ExpandMI()
2564 case ARM::VLD4d32Pseudo: in ExpandMI()
2565 case ARM::VLD1d8QPseudo: in ExpandMI()
2566 case ARM::VLD1d16QPseudo: in ExpandMI()
2567 case ARM::VLD1d32QPseudo: in ExpandMI()
2568 case ARM::VLD1d64QPseudo: in ExpandMI()
2569 case ARM::VLD1d64QPseudoWB_fixed: in ExpandMI()
2570 case ARM::VLD1d64QPseudoWB_register: in ExpandMI()
2571 case ARM::VLD1q8HighQPseudo: in ExpandMI()
2572 case ARM::VLD1q8LowQPseudo_UPD: in ExpandMI()
2573 case ARM::VLD1q8HighTPseudo: in ExpandMI()
2574 case ARM::VLD1q8LowTPseudo_UPD: in ExpandMI()
2575 case ARM::VLD1q16HighQPseudo: in ExpandMI()
2576 case ARM::VLD1q16LowQPseudo_UPD: in ExpandMI()
2577 case ARM::VLD1q16HighTPseudo: in ExpandMI()
2578 case ARM::VLD1q16LowTPseudo_UPD: in ExpandMI()
2579 case ARM::VLD1q32HighQPseudo: in ExpandMI()
2580 case ARM::VLD1q32LowQPseudo_UPD: in ExpandMI()
2581 case ARM::VLD1q32HighTPseudo: in ExpandMI()
2582 case ARM::VLD1q32LowTPseudo_UPD: in ExpandMI()
2583 case ARM::VLD1q64HighQPseudo: in ExpandMI()
2584 case ARM::VLD1q64LowQPseudo_UPD: in ExpandMI()
2585 case ARM::VLD1q64HighTPseudo: in ExpandMI()
2586 case ARM::VLD1q64LowTPseudo_UPD: in ExpandMI()
2587 case ARM::VLD4d8Pseudo_UPD: in ExpandMI()
2588 case ARM::VLD4d16Pseudo_UPD: in ExpandMI()
2589 case ARM::VLD4d32Pseudo_UPD: in ExpandMI()
2590 case ARM::VLD4q8Pseudo_UPD: in ExpandMI()
2591 case ARM::VLD4q16Pseudo_UPD: in ExpandMI()
2592 case ARM::VLD4q32Pseudo_UPD: in ExpandMI()
2593 case ARM::VLD4q8oddPseudo: in ExpandMI()
2594 case ARM::VLD4q16oddPseudo: in ExpandMI()
2595 case ARM::VLD4q32oddPseudo: in ExpandMI()
2596 case ARM::VLD4q8oddPseudo_UPD: in ExpandMI()
2597 case ARM::VLD4q16oddPseudo_UPD: in ExpandMI()
2598 case ARM::VLD4q32oddPseudo_UPD: in ExpandMI()
2599 case ARM::VLD3DUPd8Pseudo: in ExpandMI()
2600 case ARM::VLD3DUPd16Pseudo: in ExpandMI()
2601 case ARM::VLD3DUPd32Pseudo: in ExpandMI()
2602 case ARM::VLD3DUPd8Pseudo_UPD: in ExpandMI()
2603 case ARM::VLD3DUPd16Pseudo_UPD: in ExpandMI()
2604 case ARM::VLD3DUPd32Pseudo_UPD: in ExpandMI()
2605 case ARM::VLD4DUPd8Pseudo: in ExpandMI()
2606 case ARM::VLD4DUPd16Pseudo: in ExpandMI()
2607 case ARM::VLD4DUPd32Pseudo: in ExpandMI()
2608 case ARM::VLD4DUPd8Pseudo_UPD: in ExpandMI()
2609 case ARM::VLD4DUPd16Pseudo_UPD: in ExpandMI()
2610 case ARM::VLD4DUPd32Pseudo_UPD: in ExpandMI()
2611 case ARM::VLD2DUPq8EvenPseudo: in ExpandMI()
2612 case ARM::VLD2DUPq8OddPseudo: in ExpandMI()
2613 case ARM::VLD2DUPq16EvenPseudo: in ExpandMI()
2614 case ARM::VLD2DUPq16OddPseudo: in ExpandMI()
2615 case ARM::VLD2DUPq32EvenPseudo: in ExpandMI()
2616 case ARM::VLD2DUPq32OddPseudo: in ExpandMI()
2617 case ARM::VLD3DUPq8EvenPseudo: in ExpandMI()
2618 case ARM::VLD3DUPq8OddPseudo: in ExpandMI()
2619 case ARM::VLD3DUPq16EvenPseudo: in ExpandMI()
2620 case ARM::VLD3DUPq16OddPseudo: in ExpandMI()
2621 case ARM::VLD3DUPq32EvenPseudo: in ExpandMI()
2622 case ARM::VLD3DUPq32OddPseudo: in ExpandMI()
2623 case ARM::VLD4DUPq8EvenPseudo: in ExpandMI()
2624 case ARM::VLD4DUPq8OddPseudo: in ExpandMI()
2625 case ARM::VLD4DUPq16EvenPseudo: in ExpandMI()
2626 case ARM::VLD4DUPq16OddPseudo: in ExpandMI()
2627 case ARM::VLD4DUPq32EvenPseudo: in ExpandMI()
2628 case ARM::VLD4DUPq32OddPseudo: in ExpandMI()
2632 case ARM::VST2q8Pseudo: in ExpandMI()
2633 case ARM::VST2q16Pseudo: in ExpandMI()
2634 case ARM::VST2q32Pseudo: in ExpandMI()
2635 case ARM::VST2q8PseudoWB_fixed: in ExpandMI()
2636 case ARM::VST2q16PseudoWB_fixed: in ExpandMI()
2637 case ARM::VST2q32PseudoWB_fixed: in ExpandMI()
2638 case ARM::VST2q8PseudoWB_register: in ExpandMI()
2639 case ARM::VST2q16PseudoWB_register: in ExpandMI()
2640 case ARM::VST2q32PseudoWB_register: in ExpandMI()
2641 case ARM::VST3d8Pseudo: in ExpandMI()
2642 case ARM::VST3d16Pseudo: in ExpandMI()
2643 case ARM::VST3d32Pseudo: in ExpandMI()
2644 case ARM::VST1d8TPseudo: in ExpandMI()
2645 case ARM::VST1d16TPseudo: in ExpandMI()
2646 case ARM::VST1d32TPseudo: in ExpandMI()
2647 case ARM::VST1d64TPseudo: in ExpandMI()
2648 case ARM::VST3d8Pseudo_UPD: in ExpandMI()
2649 case ARM::VST3d16Pseudo_UPD: in ExpandMI()
2650 case ARM::VST3d32Pseudo_UPD: in ExpandMI()
2651 case ARM::VST1d64TPseudoWB_fixed: in ExpandMI()
2652 case ARM::VST1d64TPseudoWB_register: in ExpandMI()
2653 case ARM::VST3q8Pseudo_UPD: in ExpandMI()
2654 case ARM::VST3q16Pseudo_UPD: in ExpandMI()
2655 case ARM::VST3q32Pseudo_UPD: in ExpandMI()
2656 case ARM::VST3q8oddPseudo: in ExpandMI()
2657 case ARM::VST3q16oddPseudo: in ExpandMI()
2658 case ARM::VST3q32oddPseudo: in ExpandMI()
2659 case ARM::VST3q8oddPseudo_UPD: in ExpandMI()
2660 case ARM::VST3q16oddPseudo_UPD: in ExpandMI()
2661 case ARM::VST3q32oddPseudo_UPD: in ExpandMI()
2662 case ARM::VST4d8Pseudo: in ExpandMI()
2663 case ARM::VST4d16Pseudo: in ExpandMI()
2664 case ARM::VST4d32Pseudo: in ExpandMI()
2665 case ARM::VST1d8QPseudo: in ExpandMI()
2666 case ARM::VST1d16QPseudo: in ExpandMI()
2667 case ARM::VST1d32QPseudo: in ExpandMI()
2668 case ARM::VST1d64QPseudo: in ExpandMI()
2669 case ARM::VST4d8Pseudo_UPD: in ExpandMI()
2670 case ARM::VST4d16Pseudo_UPD: in ExpandMI()
2671 case ARM::VST4d32Pseudo_UPD: in ExpandMI()
2672 case ARM::VST1d64QPseudoWB_fixed: in ExpandMI()
2673 case ARM::VST1d64QPseudoWB_register: in ExpandMI()
2674 case ARM::VST1q8HighQPseudo: in ExpandMI()
2675 case ARM::VST1q8LowQPseudo_UPD: in ExpandMI()
2676 case ARM::VST1q8HighTPseudo: in ExpandMI()
2677 case ARM::VST1q8LowTPseudo_UPD: in ExpandMI()
2678 case ARM::VST1q16HighQPseudo: in ExpandMI()
2679 case ARM::VST1q16LowQPseudo_UPD: in ExpandMI()
2680 case ARM::VST1q16HighTPseudo: in ExpandMI()
2681 case ARM::VST1q16LowTPseudo_UPD: in ExpandMI()
2682 case ARM::VST1q32HighQPseudo: in ExpandMI()
2683 case ARM::VST1q32LowQPseudo_UPD: in ExpandMI()
2684 case ARM::VST1q32HighTPseudo: in ExpandMI()
2685 case ARM::VST1q32LowTPseudo_UPD: in ExpandMI()
2686 case ARM::VST1q64HighQPseudo: in ExpandMI()
2687 case ARM::VST1q64LowQPseudo_UPD: in ExpandMI()
2688 case ARM::VST1q64HighTPseudo: in ExpandMI()
2689 case ARM::VST1q64LowTPseudo_UPD: in ExpandMI()
2690 case ARM::VST4q8Pseudo_UPD: in ExpandMI()
2691 case ARM::VST4q16Pseudo_UPD: in ExpandMI()
2692 case ARM::VST4q32Pseudo_UPD: in ExpandMI()
2693 case ARM::VST4q8oddPseudo: in ExpandMI()
2694 case ARM::VST4q16oddPseudo: in ExpandMI()
2695 case ARM::VST4q32oddPseudo: in ExpandMI()
2696 case ARM::VST4q8oddPseudo_UPD: in ExpandMI()
2697 case ARM::VST4q16oddPseudo_UPD: in ExpandMI()
2698 case ARM::VST4q32oddPseudo_UPD: in ExpandMI()
2702 case ARM::VLD1LNq8Pseudo: in ExpandMI()
2703 case ARM::VLD1LNq16Pseudo: in ExpandMI()
2704 case ARM::VLD1LNq32Pseudo: in ExpandMI()
2705 case ARM::VLD1LNq8Pseudo_UPD: in ExpandMI()
2706 case ARM::VLD1LNq16Pseudo_UPD: in ExpandMI()
2707 case ARM::VLD1LNq32Pseudo_UPD: in ExpandMI()
2708 case ARM::VLD2LNd8Pseudo: in ExpandMI()
2709 case ARM::VLD2LNd16Pseudo: in ExpandMI()
2710 case ARM::VLD2LNd32Pseudo: in ExpandMI()
2711 case ARM::VLD2LNq16Pseudo: in ExpandMI()
2712 case ARM::VLD2LNq32Pseudo: in ExpandMI()
2713 case ARM::VLD2LNd8Pseudo_UPD: in ExpandMI()
2714 case ARM::VLD2LNd16Pseudo_UPD: in ExpandMI()
2715 case ARM::VLD2LNd32Pseudo_UPD: in ExpandMI()
2716 case ARM::VLD2LNq16Pseudo_UPD: in ExpandMI()
2717 case ARM::VLD2LNq32Pseudo_UPD: in ExpandMI()
2718 case ARM::VLD3LNd8Pseudo: in ExpandMI()
2719 case ARM::VLD3LNd16Pseudo: in ExpandMI()
2720 case ARM::VLD3LNd32Pseudo: in ExpandMI()
2721 case ARM::VLD3LNq16Pseudo: in ExpandMI()
2722 case ARM::VLD3LNq32Pseudo: in ExpandMI()
2723 case ARM::VLD3LNd8Pseudo_UPD: in ExpandMI()
2724 case ARM::VLD3LNd16Pseudo_UPD: in ExpandMI()
2725 case ARM::VLD3LNd32Pseudo_UPD: in ExpandMI()
2726 case ARM::VLD3LNq16Pseudo_UPD: in ExpandMI()
2727 case ARM::VLD3LNq32Pseudo_UPD: in ExpandMI()
2728 case ARM::VLD4LNd8Pseudo: in ExpandMI()
2729 case ARM::VLD4LNd16Pseudo: in ExpandMI()
2730 case ARM::VLD4LNd32Pseudo: in ExpandMI()
2731 case ARM::VLD4LNq16Pseudo: in ExpandMI()
2732 case ARM::VLD4LNq32Pseudo: in ExpandMI()
2733 case ARM::VLD4LNd8Pseudo_UPD: in ExpandMI()
2734 case ARM::VLD4LNd16Pseudo_UPD: in ExpandMI()
2735 case ARM::VLD4LNd32Pseudo_UPD: in ExpandMI()
2736 case ARM::VLD4LNq16Pseudo_UPD: in ExpandMI()
2737 case ARM::VLD4LNq32Pseudo_UPD: in ExpandMI()
2738 case ARM::VST1LNq8Pseudo: in ExpandMI()
2739 case ARM::VST1LNq16Pseudo: in ExpandMI()
2740 case ARM::VST1LNq32Pseudo: in ExpandMI()
2741 case ARM::VST1LNq8Pseudo_UPD: in ExpandMI()
2742 case ARM::VST1LNq16Pseudo_UPD: in ExpandMI()
2743 case ARM::VST1LNq32Pseudo_UPD: in ExpandMI()
2744 case ARM::VST2LNd8Pseudo: in ExpandMI()
2745 case ARM::VST2LNd16Pseudo: in ExpandMI()
2746 case ARM::VST2LNd32Pseudo: in ExpandMI()
2747 case ARM::VST2LNq16Pseudo: in ExpandMI()
2748 case ARM::VST2LNq32Pseudo: in ExpandMI()
2749 case ARM::VST2LNd8Pseudo_UPD: in ExpandMI()
2750 case ARM::VST2LNd16Pseudo_UPD: in ExpandMI()
2751 case ARM::VST2LNd32Pseudo_UPD: in ExpandMI()
2752 case ARM::VST2LNq16Pseudo_UPD: in ExpandMI()
2753 case ARM::VST2LNq32Pseudo_UPD: in ExpandMI()
2754 case ARM::VST3LNd8Pseudo: in ExpandMI()
2755 case ARM::VST3LNd16Pseudo: in ExpandMI()
2756 case ARM::VST3LNd32Pseudo: in ExpandMI()
2757 case ARM::VST3LNq16Pseudo: in ExpandMI()
2758 case ARM::VST3LNq32Pseudo: in ExpandMI()
2759 case ARM::VST3LNd8Pseudo_UPD: in ExpandMI()
2760 case ARM::VST3LNd16Pseudo_UPD: in ExpandMI()
2761 case ARM::VST3LNd32Pseudo_UPD: in ExpandMI()
2762 case ARM::VST3LNq16Pseudo_UPD: in ExpandMI()
2763 case ARM::VST3LNq32Pseudo_UPD: in ExpandMI()
2764 case ARM::VST4LNd8Pseudo: in ExpandMI()
2765 case ARM::VST4LNd16Pseudo: in ExpandMI()
2766 case ARM::VST4LNd32Pseudo: in ExpandMI()
2767 case ARM::VST4LNq16Pseudo: in ExpandMI()
2768 case ARM::VST4LNq32Pseudo: in ExpandMI()
2769 case ARM::VST4LNd8Pseudo_UPD: in ExpandMI()
2770 case ARM::VST4LNd16Pseudo_UPD: in ExpandMI()
2771 case ARM::VST4LNd32Pseudo_UPD: in ExpandMI()
2772 case ARM::VST4LNq16Pseudo_UPD: in ExpandMI()
2773 case ARM::VST4LNq32Pseudo_UPD: in ExpandMI()
2777 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; in ExpandMI()
2778 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; in ExpandMI()
2779 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; in ExpandMI()
2780 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; in ExpandMI()
2782 case ARM::CMP_SWAP_8: in ExpandMI()
2784 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB, in ExpandMI()
2785 ARM::tUXTB, NextMBBI); in ExpandMI()
2787 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB, in ExpandMI()
2788 ARM::UXTB, NextMBBI); in ExpandMI()
2789 case ARM::CMP_SWAP_16: in ExpandMI()
2791 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH, in ExpandMI()
2792 ARM::tUXTH, NextMBBI); in ExpandMI()
2794 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH, in ExpandMI()
2795 ARM::UXTH, NextMBBI); in ExpandMI()
2796 case ARM::CMP_SWAP_32: in ExpandMI()
2798 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0, in ExpandMI()
2801 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI); in ExpandMI()
2803 case ARM::CMP_SWAP_64: in ExpandMI()
2806 case ARM::tBL_PUSHLR: in ExpandMI()
2807 case ARM::BL_PUSHLR: { in ExpandMI()
2808 const bool Thumb = Opcode == ARM::tBL_PUSHLR; in ExpandMI()
2810 assert(Reg == ARM::LR && "expect LR register!"); in ExpandMI()
2814 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPUSH)) in ExpandMI()
2819 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tBL)); in ExpandMI()
2822 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::STMDB_UPD)) in ExpandMI()
2823 .addReg(ARM::SP, RegState::Define) in ExpandMI()
2824 .addReg(ARM::SP) in ExpandMI()
2829 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::BL)); in ExpandMI()
2836 case ARM::LOADDUAL: in ExpandMI()
2837 case ARM::STOREDUAL: { in ExpandMI()
2842 TII->get(Opcode == ARM::LOADDUAL ? ARM::LDRD : ARM::STRD)) in ExpandMI()
2843 .addReg(TRI->getSubReg(PairReg, ARM::gsub_0), in ExpandMI()
2844 Opcode == ARM::LOADDUAL ? RegState::Define : 0) in ExpandMI()
2845 .addReg(TRI->getSubReg(PairReg, ARM::gsub_1), in ExpandMI()
2846 Opcode == ARM::LOADDUAL ? RegState::Define : 0); in ExpandMI()
2876 LLVM_DEBUG(dbgs() << "********** ARM EXPAND PSEUDO INSTRUCTIONS **********\n" in runOnMachineFunction()
2883 MF.verify(this, "After expanding ARM pseudo instructions."); in runOnMachineFunction()