Lines Matching refs:ResultReg
194 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
303 Register ResultReg = createResultReg(RC); in fastEmitInst_r() local
311 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
316 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
319 return ResultReg; in fastEmitInst_r()
326 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
336 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
344 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
347 return ResultReg; in fastEmitInst_rr()
354 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
362 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_ri()
370 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_ri()
373 return ResultReg; in fastEmitInst_ri()
379 unsigned ResultReg = createResultReg(RC); in fastEmitInst_i() local
384 ResultReg).addImm(Imm)); in fastEmitInst_i()
389 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_i()
392 return ResultReg; in fastEmitInst_i()
494 unsigned ResultReg = 0; in ARMMaterializeInt() local
496 ResultReg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); in ARMMaterializeInt()
498 if (ResultReg) in ARMMaterializeInt()
499 return ResultReg; in ARMMaterializeInt()
508 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
511 TII.get(ARM::t2LDRpci), ResultReg) in ARMMaterializeInt()
515 ResultReg = constrainOperandRegClass(TII.get(ARM::LDRcp), ResultReg, 0); in ARMMaterializeInt()
517 TII.get(ARM::LDRcp), ResultReg) in ARMMaterializeInt()
521 return ResultReg; in ARMMaterializeInt()
663 unsigned ResultReg = createResultReg(RC); in fastMaterializeAlloca() local
664 ResultReg = constrainOperandRegClass(TII.get(Opc), ResultReg, 0); in fastMaterializeAlloca()
667 TII.get(Opc), ResultReg) in fastMaterializeAlloca()
670 return ResultReg; in fastMaterializeAlloca()
838 unsigned ResultReg = createResultReg(RC); in ARMSimplifyAddress() local
841 TII.get(Opc), ResultReg) in ARMSimplifyAddress()
844 Addr.Base.Reg = ResultReg; in ARMSimplifyAddress()
903 bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in ARMEmitLoad() argument
988 ResultReg = createResultReg(RC); in ARMEmitLoad()
989 assert(ResultReg > 255 && "Expected an allocated virtual register."); in ARMEmitLoad()
991 TII.get(Opc), ResultReg); in ARMEmitLoad()
1000 .addReg(ResultReg)); in ARMEmitLoad()
1001 ResultReg = MoveReg; in ARMEmitLoad()
1035 Register ResultReg; in SelectLoad() local
1036 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) in SelectLoad()
1038 updateValueMap(I, ResultReg); in SelectLoad()
1562 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP() local
1564 TII.get(Opc), ResultReg).addReg(FP)); in SelectIToFP()
1565 updateValueMap(I, ResultReg); in SelectIToFP()
1589 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); in SelectFPToI() local
1591 TII.get(Opc), ResultReg).addReg(Op)); in SelectFPToI()
1595 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
1655 unsigned ResultReg = createResultReg(RC); in SelectSelect() local
1660 ResultReg) in SelectSelect()
1668 ResultReg) in SelectSelect()
1674 updateValueMap(I, ResultReg); in SelectSelect()
1766 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectBinaryIntOp() local
1770 TII.get(Opc), ResultReg) in SelectBinaryIntOp()
1772 updateValueMap(I, ResultReg); in SelectBinaryIntOp()
1815 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); in SelectBinaryFPOp() local
1817 TII.get(Opc), ResultReg) in SelectBinaryFPOp()
1819 updateValueMap(I, ResultReg); in SelectBinaryFPOp()
2042 Register ResultReg = createResultReg(DstRC); in FinishCall() local
2044 TII.get(ARM::VMOVDRR), ResultReg) in FinishCall()
2052 updateValueMap(I, ResultReg); in FinishCall()
2063 Register ResultReg = createResultReg(DstRC); in FinishCall() local
2066 ResultReg).addReg(RVLocs[0].getLocReg()); in FinishCall()
2070 updateValueMap(I, ResultReg); in FinishCall()
2464 Register ResultReg; in ARMTryEmitSmallMemCpy() local
2465 RV = ARMEmitLoad(VT, ResultReg, Src); in ARMTryEmitSmallMemCpy()
2467 RV = ARMEmitStore(VT, ResultReg, Dest); in ARMTryEmitSmallMemCpy()
2698 unsigned ResultReg; in ARMEmitIntExt() local
2714 ResultReg = createResultReg(RC); in ARMEmitIntExt()
2721 *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg); in ARMEmitIntExt()
2731 SrcReg = ResultReg; in ARMEmitIntExt()
2734 return ResultReg; in ARMEmitIntExt()
2756 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); in SelectIntExt() local
2757 if (ResultReg == 0) return false; in SelectIntExt()
2758 updateValueMap(I, ResultReg); in SelectIntExt()
2798 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); in SelectShift() local
2799 if(ResultReg == 0) return false; in SelectShift()
2802 TII.get(Opc), ResultReg) in SelectShift()
2813 updateValueMap(I, ResultReg); in SelectShift()
2939 Register ResultReg = MI->getOperand(0).getReg(); in tryToFoldLoadIntoMI() local
2940 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) in tryToFoldLoadIntoMI()
3061 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
3064 ResultReg).addReg(DstReg, getKillRegState(true)); in fastLowerArguments()
3065 updateValueMap(&Arg, ResultReg); in fastLowerArguments()