330                         bool is64BitVector);
1915                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1917   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2072   bool is64BitVector = VT.is64BitVector();  in SelectVLD()  local
2073   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2102     if (!is64BitVector)  in SelectVLD()
2118   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2119     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLD()
2187   unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);  in SelectVLD()
2217   bool is64BitVector = VT.is64BitVector();  in SelectVST()  local
2218   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2252   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2256     } else if (is64BitVector) {  in SelectVST()
2278     unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVST()
2373   bool is64BitVector = VT.is64BitVector();  in SelectVLDSTLane()  local
2411     if (!is64BitVector)  in SelectVLDSTLane()
2437     if (is64BitVector)  in SelectVLDSTLane()
2446     if (is64BitVector)  in SelectVLDSTLane()
2457   unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLDSTLane()
2471   unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDSTLane()
2906   bool is64BitVector = VT.is64BitVector();  in SelectVLDDup()  local
2944   if (!is64BitVector)  in SelectVLDDup()
2958   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
2962     unsigned Opc = is64BitVector ? DOpcodes[OpcodeIndex] :  in SelectVLDDup()
3013     unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;  in SelectVLDDup()