Lines Matching refs:RdHi
4230 bits<4> RdHi;
4233 let Inst{19-16} = RdHi;
4242 bits<4> RdHi;
4245 let Inst{19-16} = RdHi;
4312 def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
4314 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4315 [(set GPR:$RdLo, GPR:$RdHi,
4320 def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
4322 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4323 [(set GPR:$RdLo, GPR:$RdHi,
4328 let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
4329 def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4332 [(set GPR:$RdLo, GPR:$RdHi,
4334 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4338 def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4341 [(set GPR:$RdLo, GPR:$RdHi,
4343 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4350 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4352 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4353 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4355 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4357 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4358 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4361 def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
4364 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4365 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4368 bits<4> RdHi;
4371 let Inst{19-16} = RdHi;
4378 "@earlyclobber $RdLo,@earlyclobber $RdHi,$RLo = $RdLo,$RHi = $RdHi" in {
4379 def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4382 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4386 def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
4389 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4538 (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4540 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4541 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4595 bits<4> RdHi;
4596 let Inst{19-16} = RdHi;
4612 def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4615 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4616 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
4619 def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
4622 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4623 RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
6345 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6346 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6348 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6349 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6351 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6352 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6354 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6355 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,