Lines Matching refs:Vd
264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
305 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
315 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
325 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
335 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
367 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
377 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
387 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
408 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
418 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
428 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
438 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
600 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
602 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
608 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
610 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
628 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
630 "vld1", Dt, "$Vd, $Rn!",
636 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
638 "vld1", Dt, "$Vd, $Rn, $Rm",
645 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
647 "vld1", Dt, "$Vd, $Rn!",
653 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
655 "vld1", Dt, "$Vd, $Rn, $Rm",
673 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
675 "$Vd, $Rn", "", []>, Sched<[WriteVLD3]> {
681 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
683 "vld1", Dt, "$Vd, $Rn!",
689 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
691 "vld1", Dt, "$Vd, $Rn, $Rm",
726 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
728 "$Vd, $Rn", "", []>, Sched<[WriteVLD4]> {
734 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
736 "vld1", Dt, "$Vd, $Rn!",
742 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
744 "vld1", Dt, "$Vd, $Rn, $Rm",
780 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
782 "vld2", Dt, "$Vd, $Rn", "", []> {
809 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
811 "vld2", Dt, "$Vd, $Rn!",
817 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
819 "vld2", Dt, "$Vd, $Rn, $Rm",
863 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
865 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []>, Sched<[WriteVLD3]> {
882 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
884 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
922 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
924 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []>,
942 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
944 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
1011 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1013 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1014 "$src = $Vd",
1015 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1023 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1025 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1026 "$src = $Vd",
1027 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1097 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1100 "\\{$Vd[$lane]\\}, $Rn$Rm",
1101 "$src = $Vd, $Rn.addr = $wb", []>, Sched<[WriteVLD1]> {
1124 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1126 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1127 "$src1 = $Vd, $src2 = $dst2", []>, Sched<[WriteVLD1]> {
1160 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1163 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1164 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1195 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1198 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1199 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []>, Sched<[WriteVLD2]> {
1232 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1236 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1237 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1269 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1272 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1273 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []>,
1310 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1314 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1315 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1352 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1354 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1355 [(set VecListOneDAllLanes:$Vd,
1376 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1378 "vld1", Dt, "$Vd, $Rn", "",
1379 [(set VecListDPairAllLanes:$Vd,
1402 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1404 "vld1", Dt, "$Vd, $Rn!",
1411 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1413 "vld1", Dt, "$Vd, $Rn, $Rm",
1421 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1423 "vld1", Dt, "$Vd, $Rn!",
1430 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1432 "vld1", Dt, "$Vd, $Rn, $Rm",
1449 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1451 "vld2", Dt, "$Vd, $Rn", "", []> {
1485 (outs VdTy:$Vd, GPR:$wb),
1487 "vld2", Dt, "$Vd, $Rn!",
1494 (outs VdTy:$Vd, GPR:$wb),
1496 "vld2", Dt, "$Vd, $Rn, $Rm",
1519 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1521 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []>,
1550 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1552 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1573 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1575 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1604 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1606 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1668 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1669 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST1]> {
1675 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1676 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST2]> {
1695 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1696 "vst1", Dt, "$Vd, $Rn!",
1703 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1705 "vst1", Dt, "$Vd, $Rn, $Rm",
1713 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1714 "vst1", Dt, "$Vd, $Rn!",
1721 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1723 "vst1", Dt, "$Vd, $Rn, $Rm",
1743 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1744 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVST3]> {
1751 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1752 "vst1", Dt, "$Vd, $Rn!",
1759 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1761 "vst1", Dt, "$Vd, $Rn, $Rm",
1797 (ins AddrMode:$Rn, VecListFourD:$Vd),
1798 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1806 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1807 "vst1", Dt, "$Vd, $Rn!",
1814 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1816 "vst1", Dt, "$Vd, $Rn, $Rm",
1852 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1853 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1881 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1882 "vst2", Dt, "$Vd, $Rn!",
1889 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1890 "vst2", Dt, "$Vd, $Rn, $Rm",
1898 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1899 "vst2", Dt, "$Vd, $Rn!",
1906 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1908 "vst2", Dt, "$Vd, $Rn, $Rm",
1950 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1951 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []>, Sched<[WriteVST3]> {
1969 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1970 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
2008 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
2009 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
2028 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
2029 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
2094 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2095 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2096 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]>,
2144 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2145 "\\{$Vd[$lane]\\}, $Rn$Rm",
2147 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2182 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2183 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2221 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2222 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2255 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2257 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []>,
2292 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2294 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2326 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2328 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2366 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2368 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2451 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2452 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2453 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2457 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2458 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2459 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2466 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2467 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2473 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2474 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2475 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2481 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2483 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2488 : N2Vnp<op19_18, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2490 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2496 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2498 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2500 // Same as N2VQIntXnp but with Vd as a src register.
2505 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2507 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2508 let Constraints = "$src = $Vd";
2516 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2517 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2518 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2525 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2526 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2527 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2534 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2535 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2536 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2543 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2544 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2545 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2549 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2551 OpcodeStr, Dt, "$Vd, $Vm",
2552 "$src1 = $Vd, $src2 = $Vm", []>;
2555 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2556 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2557 "$src1 = $Vd, $src2 = $Vm", []>;
2564 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2565 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2566 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2568 let TwoOperandAliasConstraint = "$Vn = $Vd";
2577 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2578 OpcodeStr, "$Vd, $Vn, $Vm", "",
2579 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2581 let TwoOperandAliasConstraint = "$Vn = $Vd";
2589 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2590 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2591 [(set (Ty DPR:$Vd),
2595 let TwoOperandAliasConstraint = "$Vn = $Vd";
2601 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2602 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2603 [(set (Ty DPR:$Vd),
2607 let TwoOperandAliasConstraint = "$Vn = $Vd";
2615 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2616 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2617 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2619 let TwoOperandAliasConstraint = "$Vn = $Vd";
2626 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2627 OpcodeStr, "$Vd, $Vn, $Vm", "",
2628 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2630 let TwoOperandAliasConstraint = "$Vn = $Vd";
2637 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2638 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2639 [(set (ResTy QPR:$Vd),
2644 let TwoOperandAliasConstraint = "$Vn = $Vd";
2650 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2651 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2652 [(set (ResTy QPR:$Vd),
2657 let TwoOperandAliasConstraint = "$Vn = $Vd";
2666 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2667 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2668 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2670 let TwoOperandAliasConstraint = "$Vn = $Vd";
2679 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2680 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2685 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2686 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2687 [(set (Ty DPR:$Vd),
2697 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2698 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2699 [(set (Ty DPR:$Vd),
2708 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2709 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2710 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2711 let TwoOperandAliasConstraint = "$Vm = $Vd";
2719 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2720 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2721 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2723 let TwoOperandAliasConstraint = "$Vn = $Vd";
2732 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2733 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2735 // Same as N3VQIntnp but with Vd as a src register.
2741 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
2743 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2745 let Constraints = "$src = $Vd";
2752 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2753 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2754 [(set (ResTy QPR:$Vd),
2764 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2765 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2766 [(set (ResTy QPR:$Vd),
2776 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2777 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2778 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2779 let TwoOperandAliasConstraint = "$Vm = $Vd";
2788 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2789 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2790 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2797 (outs DPR:$Vd),
2800 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2801 [(set (Ty DPR:$Vd),
2810 (outs DPR:$Vd),
2813 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2814 [(set (Ty DPR:$Vd),
2824 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2825 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2826 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2832 (outs QPR:$Vd),
2835 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2836 [(set (ResTy QPR:$Vd),
2846 (outs QPR:$Vd),
2849 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2850 [(set (ResTy QPR:$Vd),
2861 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2862 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2863 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2869 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2870 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2871 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2880 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2881 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2882 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2888 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2889 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2890 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2898 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2899 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2900 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2906 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2909 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2910 [(set QPR:$Vd,
2918 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2921 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2922 [(set QPR:$Vd,
2934 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2935 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2936 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2946 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2947 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2948 [(set QPR:$Vd,
2954 (outs QPR:$Vd),
2957 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2958 [(set (ResTy QPR:$Vd),
2967 (outs QPR:$Vd),
2970 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2971 [(set (ResTy QPR:$Vd),
2982 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2983 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2984 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2993 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2994 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2995 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3003 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3004 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3005 [(set QPR:$Vd,
3012 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3013 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3014 [(set QPR:$Vd,
3024 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3025 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3026 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
3037 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3038 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3039 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
3049 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3050 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3051 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
3061 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
3062 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3068 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3069 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3070 [(set (ResTy QPR:$Vd),
3078 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3079 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3080 [(set (ResTy QPR:$Vd),
3090 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3091 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3092 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3095 let TwoOperandAliasConstraint = "$Vn = $Vd";
3104 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3105 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3106 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3111 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3112 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3113 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3123 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3124 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3125 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3131 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3132 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3133 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3137 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3142 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3143 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3144 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3149 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3150 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3151 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3160 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3161 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3162 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3170 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3171 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3172 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3177 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3181 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3183 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3184 [(set DPR:$Vd, (Ty (add DPR:$src1,
3189 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3191 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3192 [(set QPR:$Vd, (Ty (add QPR:$src1,
3198 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3202 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3204 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3205 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3209 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3211 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3212 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3221 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3222 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3223 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3228 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3229 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3230 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3251 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3253 [(set DPR:$Vd, (v8i8 (ARMvcmpz (v8i8 DPR:$Vm), fc)))]>;
3255 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3257 [(set DPR:$Vd, (v4i16 (ARMvcmpz (v4i16 DPR:$Vm), fc)))]>;
3259 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3261 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2i32 DPR:$Vm), fc)))]>;
3263 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3265 [(set DPR:$Vd, (v2i32 (ARMvcmpz (v2f32 DPR:$Vm), fc)))]> {
3269 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3271 [(set DPR:$Vd, (v4i16 (ARMvcmpz (v4f16 DPR:$Vm), fc)))]>,
3278 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3280 [(set QPR:$Vd, (v16i8 (ARMvcmpz (v16i8 QPR:$Vm), fc)))]>;
3282 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3284 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8i16 QPR:$Vm), fc)))]>;
3286 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3288 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4i32 QPR:$Vm), fc)))]>;
3290 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3292 [(set QPR:$Vd, (v4i32 (ARMvcmpz (v4f32 QPR:$Vm), fc)))]> {
3296 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3298 [(set QPR:$Vd, (v8i16 (ARMvcmpz (v8f16 QPR:$Vm), fc)))]>,
3309 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
3310 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3311 [(set QPR:$Vd, (ResTy (ARMvcmp (OpTy QPR:$Vn), (OpTy QPR:$Vm), fc)))]> {
3313 let TwoOperandAliasConstraint = "$Vn = $Vd";
3321 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
3322 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3323 [(set DPR:$Vd, (ResTy (ARMvcmp (OpTy DPR:$Vn), (OpTy DPR:$Vm), fc)))]> {
3325 let TwoOperandAliasConstraint = "$Vn = $Vd";
4771 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4774 (OpNode (AccumTy RegTy:$Vd),
4779 let Constraints = "$dst = $Vd";
4792 (ins Ty:$Vd, Ty:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
4796 let AsmString = !strconcat(opc, ".", dt, "\t$Vd, $Vn, $Vm$lane");
4797 let Constraints = "$dst = $Vd";
4803 (AccumType (OpNode (AccumType Ty:$Vd),
4808 (!cast<Instruction>(NAME) Ty:$Vd, Ty:$Vn, RHS, VectorIndex32:$lane)>;
4825 (ins QPR:$Vd, QPR:$Vn, QPR:$Vm), N3RegFrm, NoItinerary,
4827 [(set (v4i32 QPR:$dst), (OpNode (v4i32 QPR:$Vd),
4831 let Constraints = "$dst = $Vd";
4839 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
4843 let AsmString = !strconcat(Asm, ".", AsmTy, "\t$Vd, $Vn, $Vm$lane");
4845 let Constraints = "$dst = $Vd";
4849 (AccumTy (OpNode (AccumTy RegTy:$Vd),
4854 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4861 (AccumTy (int_arm_neon_usdot (AccumTy RegTy:$Vd),
4866 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
4888 iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "$src1 = $Vd", pattern>{
4897 iops, itin, opc, dt, "$Vd, $Vn, $Vm, $rot", "", pattern> {
4906 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4918 "$Vd, $Vn, $Vm$lane, $rot", "$src1 = $Vd", pattern> {
4933 def v4f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
4936 def v8f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 1, IIC_VMACQ, (outs QPR:$Vd),
4941 def v2f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 0, IIC_VMACD, (outs DPR:$Vd),
4944 def v4f32 : BaseN3VCP8ComplexTied<op21, op4, 1, 1, IIC_VMACQ, (outs QPR:$Vd),
4954 (outs DPR:$Vd),
4958 (outs QPR:$Vd),
4964 (outs DPR:$Vd),
4968 (outs QPR:$Vd),
4980 (outs DPR:$Vd),
4985 (outs QPR:$Vd),
4992 (outs DPR:$Vd),
4997 (outs QPR:$Vd),
5097 let TwoOperandAliasConstraint = "$Vm = $Vd" in
5099 "$Vd, $Vm, #0", ARMCCeq>;
5117 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
5119 "$Vd, $Vm, #0", ARMCCge>;
5121 "$Vd, $Vm, #0", ARMCCle>;
5140 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
5142 "$Vd, $Vm, #0", ARMCCgt>;
5144 "$Vd, $Vm, #0", ARMCClt>;
5173 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
5174 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5175 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
5176 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5177 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
5178 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5179 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
5180 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5182 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
5183 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5184 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vn, $Vm",
5185 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5186 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
5187 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
5188 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vn, $Vm",
5189 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
5197 : N3VCP8<op1, op2, 1, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5198 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5202 : N3VCP8Q0<op1, op2, 0, op3, (outs Td:$Vd), (ins Tn:$Vn, Tm:$Vm), NoItinerary,
5203 asm, "f16", "$Vd, $Vn, $Vm", "", []>;
5205 // Vd, Vs, Vs[0-15], Idx[0-1]
5207 : N3VLaneCP8<0, S, 0, 1, (outs DPR:$Vd),
5209 IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
5218 // Vq, Vd, Vd[0-7], Idx[0-3]
5220 : N3VLaneCP8<0, S, 1, 1, (outs QPR:$Vd),
5222 IIC_VMACD, opc, type, "$Vd, $Vn, $Vm$idx", "", []> {
5240 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
5241 (VACGTfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5242 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
5243 (VACGTfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5244 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
5245 (VACGEfd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5246 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
5247 (VACGEfq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5249 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
5250 (VACGThd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5251 def: NEONInstAlias<"vaclt${p}.f16 $Vd, $Vm",
5252 (VACGThq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5253 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
5254 (VACGEhd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
5255 def: NEONInstAlias<"vacle${p}.f16 $Vd, $Vm",
5256 (VACGEhq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
5286 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
5288 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
5289 [(set DPR:$Vd,
5295 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
5297 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
5298 [(set DPR:$Vd,
5304 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5306 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
5307 [(set QPR:$Vd,
5313 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5315 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
5316 [(set QPR:$Vd,
5323 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5324 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5326 "vbic", "$Vd, $Vn, $Vm", "",
5327 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
5329 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5331 "vbic", "$Vd, $Vn, $Vm", "",
5332 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
5337 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
5339 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
5340 [(set DPR:$Vd,
5346 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
5348 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
5349 [(set DPR:$Vd,
5355 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
5357 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
5358 [(set QPR:$Vd,
5364 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
5366 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
5367 [(set QPR:$Vd,
5373 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
5375 "vorn", "$Vd, $Vn, $Vm", "",
5376 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
5378 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5380 "vorn", "$Vd, $Vn, $Vm", "",
5381 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
5388 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
5390 "vmvn", "i16", "$Vd, $SIMM", "",
5391 [(set DPR:$Vd, (v4i16 (ARMvmvnImm timm:$SIMM)))]> {
5395 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
5397 "vmvn", "i16", "$Vd, $SIMM", "",
5398 [(set QPR:$Vd, (v8i16 (ARMvmvnImm timm:$SIMM)))]> {
5402 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
5404 "vmvn", "i32", "$Vd, $SIMM", "",
5405 [(set DPR:$Vd, (v2i32 (ARMvmvnImm timm:$SIMM)))]> {
5409 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
5411 "vmvn", "i32", "$Vd, $SIMM", "",
5412 [(set QPR:$Vd, (v4i32 (ARMvmvnImm timm:$SIMM)))]> {
5419 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
5420 "vmvn", "$Vd, $Vm", "",
5421 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
5423 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
5424 "vmvn", "$Vd, $Vm", "",
5425 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
5436 : PseudoNeonI<(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5438 [(set DPR:$Vd,
5457 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
5458 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5459 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5461 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
5462 (and DPR:$Vm, (vnotd DPR:$Vd)))),
5463 (VBSPd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
5467 : PseudoNeonI<(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5469 [(set QPR:$Vd,
5488 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
5489 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5490 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5491 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
5492 (and QPR:$Vm, (vnotq QPR:$Vd)))),
5493 (VBSPq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
5497 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5500 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5503 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5506 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5512 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5514 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5517 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5519 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5525 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
5527 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
5530 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
5532 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
6048 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
6049 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
6050 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
6052 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
6053 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
6054 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
6066 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
6067 "vneg", "f32", "$Vd, $Vm", "",
6068 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
6070 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6071 "vneg", "f32", "$Vd, $Vm", "",
6072 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
6074 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
6075 "vneg", "f16", "$Vd, $Vm", "",
6076 [(set DPR:$Vd, (v4f16 (fneg DPR:$Vm)))]>,
6079 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
6080 "vneg", "f16", "$Vd, $Vm", "",
6081 [(set QPR:$Vd, (v8f16 (fneg QPR:$Vm)))]>,
6118 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
6119 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6122 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
6123 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
6129 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
6130 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
6131 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
6132 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
6140 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
6142 "vmov", "i8", "$Vd, $SIMM", "",
6143 [(set DPR:$Vd, (v8i8 (ARMvmovImm timm:$SIMM)))]>;
6144 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
6146 "vmov", "i8", "$Vd, $SIMM", "",
6147 [(set QPR:$Vd, (v16i8 (ARMvmovImm timm:$SIMM)))]>;
6149 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
6151 "vmov", "i16", "$Vd, $SIMM", "",
6152 [(set DPR:$Vd, (v4i16 (ARMvmovImm timm:$SIMM)))]> {
6156 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
6158 "vmov", "i16", "$Vd, $SIMM", "",
6159 [(set QPR:$Vd, (v8i16 (ARMvmovImm timm:$SIMM)))]> {
6163 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
6165 "vmov", "i32", "$Vd, $SIMM", "",
6166 [(set DPR:$Vd, (v2i32 (ARMvmovImm timm:$SIMM)))]> {
6170 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
6172 "vmov", "i32", "$Vd, $SIMM", "",
6173 [(set QPR:$Vd, (v4i32 (ARMvmovImm timm:$SIMM)))]> {
6177 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
6179 "vmov", "i64", "$Vd, $SIMM", "",
6180 [(set DPR:$Vd, (v1i64 (ARMvmovImm timm:$SIMM)))]>;
6181 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
6183 "vmov", "i64", "$Vd, $SIMM", "",
6184 [(set QPR:$Vd, (v2i64 (ARMvmovImm timm:$SIMM)))]>;
6186 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
6188 "vmov", "f32", "$Vd, $SIMM", "",
6189 [(set DPR:$Vd, (v2f32 (ARMvmovFPImm timm:$SIMM)))]>;
6190 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
6192 "vmov", "f32", "$Vd, $SIMM", "",
6193 [(set QPR:$Vd, (v4f32 (ARMvmovFPImm timm:$SIMM)))]>;
6205 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6206 (VMOVv8i8 DPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6207 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6208 (VMOVv16i8 QPR:$Vd, nImmVMOVIReplicate<i8, To>:$Vm, pred:$p)>;
6213 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6214 (VMOVv8i8 DPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6215 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6216 (VMOVv16i8 QPR:$Vd, nImmVINVIReplicate<i8, To>:$Vm, pred:$p)>;
6229 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6230 (V8 DPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6231 def : NEONInstAlias<"vmov${p}.i" # To.Size # " $Vd, $Vm",
6232 (V16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6233 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6234 (NV8 DPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6235 def : NEONInstAlias<"vmvn${p}.i" # To.Size # " $Vd, $Vm",
6236 (NV16 QPR:$Vd, nImmVMOVIReplicate<From, To>:$Vm, pred:$p)>;
6258 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
6259 [(set DPR:$Vd, (v2i32 ARMimmAllZerosD))],
6260 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
6262 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
6263 [(set QPR:$Vd, (v4i32 ARMimmAllZerosV))],
6264 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
6556 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6557 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
6558 [(set DPR:$Vd, (Ty (ARMvduplane (Ty DPR:$Vm), imm:$lane)))]>;
6562 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
6563 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
6564 [(set QPR:$Vd, (ResTy (ARMvduplane (OpTy DPR:$Vm),
6850 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
6852 OpcodeStr, Dt, "$Vd, $Vm", "",
6853 [(set DPR:$Vd, (Ty (ARMvrev64 (Ty DPR:$Vm))))]>;
6855 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
6857 OpcodeStr, Dt, "$Vd, $Vm", "",
6858 [(set QPR:$Vd, (Ty (ARMvrev64 (Ty QPR:$Vm))))]>;
6883 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
6885 OpcodeStr, Dt, "$Vd, $Vm", "",
6886 [(set DPR:$Vd, (Ty (ARMvrev32 (Ty DPR:$Vm))))]>;
6888 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
6890 OpcodeStr, Dt, "$Vd, $Vm", "",
6891 [(set QPR:$Vd, (Ty (ARMvrev32 (Ty QPR:$Vm))))]>;
6909 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
6911 OpcodeStr, Dt, "$Vd, $Vm", "",
6912 [(set DPR:$Vd, (Ty (ARMvrev16 (Ty DPR:$Vm))))]>;
6914 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
6916 OpcodeStr, Dt, "$Vd, $Vm", "",
6917 [(set QPR:$Vd, (Ty (ARMvrev16 (Ty QPR:$Vm))))]>;
6947 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
6949 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
6951 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
6952 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
6960 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
6962 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
6963 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
7055 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
7057 "vtbl", "8", "$Vd, $Vn, $Vm", "",
7058 [(set DPR:$Vd, (v8i8 (NEONvtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
7062 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
7064 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7066 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
7068 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7070 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
7073 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
7083 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
7085 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
7086 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
7090 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
7092 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
7094 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
7097 "vtbx", "8", "$Vd, $Vn, $Vm",
7098 "$orig = $Vd", []>;
7100 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
7102 "vtbx", "8", "$Vd, $Vn, $Vm",
7103 "$orig = $Vd", []>;
7997 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
7998 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7999 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
8000 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8001 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
8002 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8003 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
8004 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8005 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
8006 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8007 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
8008 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8009 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
8010 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8011 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
8012 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8027 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
8028 (VBICiv4i16 DPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8029 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
8030 (VBICiv2i32 DPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8031 def : NEONInstAlias<"vand${p}.i16 $Vd, $imm",
8032 (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)>;
8033 def : NEONInstAlias<"vand${p}.i32 $Vd, $imm",
8034 (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)>;
8873 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8874 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
8875 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
8876 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
8878 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
8879 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
8880 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
8881 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
8960 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8961 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
8962 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8963 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
8966 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
8967 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8968 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
8969 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8970 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
8971 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
8972 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
8973 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8974 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
8975 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8976 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
8977 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
8980 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
8981 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8982 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
8983 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8984 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
8985 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
8986 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
8987 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
9033 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
9034 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9035 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
9036 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
9050 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9052 (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
9055 let Constraints = "$dst = $Vd";
9056 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
9064 (ins RegTy:$Vd, RegTy:$Vn,
9068 let Constraints = "$dst = $Vd";
9069 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm$lane");
9074 (AccumTy (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
9079 (!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
9091 (outs RegTy:$dst), (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
9093 [(set (v4f32 QPR:$dst), (int_arm_neon_bfmmla (v4f32 QPR:$Vd),
9096 let Constraints = "$dst = $Vd";
9097 let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
9105 (outs QPR:$dst), (ins QPR:$Vd, QPR:$Vn, QPR:$Vm),
9106 NoItinerary, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm", "",
9108 (OpNode (v4f32 QPR:$Vd),
9111 let Constraints = "$dst = $Vd";
9120 (ins QPR:$Vd, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
9121 IIC_VMACD, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm$idx", "", []> {
9125 let Constraints = "$dst = $Vd";
9130 (v4f32 (OpNode (v4f32 QPR:$Vd),
9134 (!cast<Instruction>(NAME) QPR:$Vd,
9145 (outs DPR:$Vd), (ins QPR:$Vm),
9146 NoItinerary, "vcvt", "bf16.f32", "$Vd, $Vm", "", []>;