Lines Matching refs:b0001
959 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
960 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
961 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
962 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
963 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
964 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
1133 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1169 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
2044 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
2045 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
2046 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
2047 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
2048 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
2049 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
2190 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2228 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
4202 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4203 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4212 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4215 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4404 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4407 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4410 def VMLAslhd : N3VDMulOpSL16<0b01, 0b0001, IIC_VMACD, "vmla", "f16",
4413 def VMLAslhq : N3VQMulOpSL16<0b01, 0b0001, IIC_VMACQ, "vmla", "f16",
5268 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
5270 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
5274 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
5276 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
5280 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
5282 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
5324 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5329 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5373 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
5378 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
5497 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
5503 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
5511 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
5516 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
5524 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
5529 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
6003 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", ARMvshrsImm>;
6004 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", ARMvshruImm>;