Lines Matching refs:b1011

1286 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1299 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1327 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1339 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2341 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2354 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2380 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2392 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4314 defm VQDMULH  : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4339 defm VQRDMULH   : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4382 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4458   defm VQRDMLAH : N3VInt3_HS<1, 0, 0b1011, 1, IIC_VMACi16D, IIC_VMACi32D,
4688 defm VQDMLSL  : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
5685 def  VPADDi8  : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5688 def  VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
5691 def  VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
6270 def VGETLNs8  : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
6278 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
6286 def VGETLNu8  : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
6294 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
6302 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
6412 def VSETLNi8  : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
6420 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
6428 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
6524   : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
6528   : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
7070   : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
7100   : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),