Lines Matching refs:Rd
439 bits<4> Rd;
442 let Inst{11-8} = Rd;
452 bits<4> Rd;
456 let Inst{11-8} = Rd;
478 bits<4> Rd;
481 let Inst{11-8} = Rd;
491 bits<4> Rd;
494 let Inst{11-8} = Rd;
517 bits<4> Rd;
520 let Inst{11-8} = Rd;
527 bits<4> Rd;
530 let Inst{11-8} = Rd;
548 bits<4> Rd;
552 let Inst{11-8} = Rd;
562 bits<4> Rd;
566 let Inst{11-8} = Rd;
576 bits<4> Rd;
580 let Inst{11-8} = Rd;
589 bits<4> Rd;
593 let Inst{11-8} = Rd;
602 bits<4> Rd;
606 let Inst{11-8} = Rd;
614 bits<4> Rd;
618 let Inst{11-8} = Rd;
626 bits<4> Rd;
630 let Inst{11-8} = Rd;
638 bits<4> Rd;
642 let Inst{11-8} = Rd;
653 bits<4> Rd;
657 let Inst{11-8} = Rd;
668 bits<4> Rd;
675 let Inst{11-8} = Rd;
727 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii,
728 opc, "\t$Rd, $Rn, $imm",
729 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]>,
737 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir,
738 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"),
739 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
762 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis,
763 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"),
764 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]>,
795 def : t2InstAlias<!strconcat(opc, "${s}${p}.w", " $Rd, $Rn, $imm"),
796 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p,
799 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
800 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
802 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"),
803 (!cast<Instruction>(NAME#"rs") rGPR:$Rd, rGPR:$Rn, t2_so_reg:$shift,
824 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
825 opc, ".w\t$Rd, $Rn, $imm",
826 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]>,
835 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
836 opc, "\t$Rd, $Rn, $Rm",
848 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
849 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm",
850 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>,
868 def ri : t2PseudoInst<(outs rGPR:$Rd),
871 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
875 def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
883 def rs : t2PseudoInst<(outs rGPR:$Rd),
886 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
897 def ri : t2PseudoInst<(outs rGPR:$Rd),
900 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
904 def rs : t2PseudoInst<(outs rGPR:$Rd),
907 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
922 (outs GPRsp:$Rd), (ins GPRsp:$Rn, t2_so_imm:$imm), IIC_iALUi,
923 opc, ".w\t$Rd, $Rn, $imm",
927 let Rd = 13;
938 (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi,
939 opc, ".w\t$Rd, $Rn, $imm",
940 [(set rGPR:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>,
951 (outs rGPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi,
952 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
953 [(set rGPR:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]>,
955 bits<4> Rd;
966 let Inst{11-8} = Rd;
970 (outs GPRsp:$Rd), (ins GPRsp:$Rn, imm0_4095:$imm), IIC_iALUi,
971 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm",
974 bits<4> Rd = 13;
985 let Inst{11-8} = Rd;
990 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm),
991 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm",
992 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]>,
1005 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm),
1006 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1007 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>,
1023 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm),
1024 IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1025 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
1033 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr,
1034 opc, ".w\t$Rd, $Rn, $Rm",
1035 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
1047 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
1048 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm",
1049 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
1063 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi,
1064 opc, ".w\t$Rd, $Rm, $imm",
1065 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]>,
1075 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr,
1076 opc, ".w\t$Rd, $Rn, $Rm",
1077 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]>,
1095 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"),
1096 (!cast<Instruction>(NAME#"ri") rGPR:$Rd, rGPR:$Rn, ty:$imm, pred:$p,
1098 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"),
1099 (!cast<Instruction>(NAME#"rr") rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p,
1128 let Inst{11-8} = 0b1111; // Rd
1140 let Inst{11-8} = 0b1111; // Rd
1154 let Inst{11-8} = 0b1111; // Rd
1340 (outs rGPR:$Rd),
1342 opc, ".w\t$Rd, $Rm$rot", []>,
1349 (outs rGPR:$Rd),
1351 opc, "\t$Rd, $Rm$rot", []>,
1358 : T2ThreeReg<(outs rGPR:$Rd),
1360 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1383 bits<4> Rd;
1386 let Inst{11-8} = Rd;
1394 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd),
1396 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []>,
1406 bits<4> Rd;
1408 let Inst{11-8} = Rd;
1419 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p),
1422 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd),
2106 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rm), IIC_iMOVr,
2107 "mov", ".w\t$Rd, $Rm", []>, Sched<[WriteALU]> {
2116 def : t2InstAlias<"mov${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2118 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2120 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm,
2126 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi,
2127 "mov", ".w\t$Rd, $imm",
2128 [(set rGPR:$Rd, t2_so_imm:$imm)]>, Sched<[WriteALU]> {
2138 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2140 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2143 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2145 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
2149 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
2150 "movw", "\t$Rd, $imm",
2151 [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
2159 bits<4> Rd;
2162 let Inst{11-8} = Rd;
2170 def : InstAlias<"mov${p} $Rd, $imm",
2171 (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p), 0>,
2174 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
2178 let Constraints = "$src = $Rd" in {
2179 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
2181 "movt", "\t$Rd, $imm",
2182 [(set rGPR:$Rd,
2192 bits<4> Rd;
2195 let Inst{11-8} = Rd;
2203 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
2355 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2356 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2367 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2368 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2422 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
2423 NoItinerary, "sel", "\t$Rd, $Rn, $Rm",
2424 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2439 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
2447 bits<4> Rd;
2451 let Inst{11-8} = Rd;
2459 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))],
2460 (ins rGPR:$Rn, rGPR:$Rm), "\t$Rd, $Rn, $Rm">;
2464 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">;
2564 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2566 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm",
2567 [(set rGPR:$Rd, (int_arm_usad8 rGPR:$Rn, rGPR:$Rm))]>,
2571 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
2573 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
2574 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
2579 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, []> {
2580 bits<4> Rd;
2591 let Inst{11-8} = Rd;
2598 "ssat", "\t$Rd, $sat_imm, $Rn$sh">,
2605 "ssat16", "\t$Rd, $sat_imm, $Rn">,
2613 "usat", "\t$Rd, $sat_imm, $Rn$sh">,
2619 "usat16", "\t$Rd, $sat_imm, $Rn">,
2667 def : t2InstAlias<"lsl${s}${p} $Rd, $Rm, #0",
2668 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2669 def : t2InstAlias<"lsl${s}${p}.w $Rd, $Rm, #0",
2670 (t2MOVr GPRnopc:$Rd, GPRnopc:$Rm, pred:$p, cc_out:$s)>;
2677 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2678 "rrx", "\t$Rd, $Rm",
2679 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]>, Sched<[WriteALU]> {
2693 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2694 "lsrs", ".w\t$Rd, $Rm, #1",
2695 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]>,
2708 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi,
2709 "asrs", ".w\t$Rd, $Rm, #1",
2710 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]>,
2742 bits<4> Rd;
2746 let Inst{11-8} = Rd;
2760 let Constraints = "$src = $Rd" in
2761 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
2762 IIC_iUNAsi, "bfc", "\t$Rd, $imm",
2763 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]>, Sched<[WriteALU]> {
2778 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2779 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2789 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
2790 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []>, Sched<[WriteALU]> {
2813 let Constraints = "$src = $Rd" in {
2814 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd),
2816 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm",
2817 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn,
2844 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii,
2845 opc, "\t$Rd, $imm",
2846 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]>, Sched<[WriteALU]> {
2857 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir,
2858 opc, ".w\t$Rd, $Rm",
2859 [(set rGPR:$Rd, (opnode rGPR:$Rm))]>, Sched<[WriteALU]> {
2869 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis,
2870 opc, ".w\t$Rd, $ShiftedRm",
2871 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]>,
2926 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
2927 "mul", "\t$Rd, $Rn, $Rm",
2928 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]>,
2938 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2939 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
2949 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm),
2952 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
2976 : T2ThreeReg<(outs rGPR:$Rd),
2978 opc, "\t$Rd, $Rn, $Rm", pattern>,
2987 def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
2991 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, (i32 0)))]>;
2995 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
2996 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3006 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>;
3008 [(set rGPR:$Rd, (ARMsmmlar rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
3011 [(set rGPR:$Rd, (ARMsmmlsr rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>;
3015 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
3016 "\t$Rd, $Rn, $Rm", pattern>,
3028 [(set rGPR:$Rd, (bb_mul rGPR:$Rn, rGPR:$Rm))]>;
3030 [(set rGPR:$Rd, (bt_mul rGPR:$Rn, rGPR:$Rm))]>;
3032 [(set rGPR:$Rd, (tb_mul rGPR:$Rn, rGPR:$Rm))]>;
3034 [(set rGPR:$Rd, (tt_mul rGPR:$Rn, rGPR:$Rm))]>;
3036 [(set rGPR:$Rd, (ARMsmulwb rGPR:$Rn, rGPR:$Rm))]>;
3038 [(set rGPR:$Rd, (ARMsmulwt rGPR:$Rn, rGPR:$Rm))]>;
3062 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
3063 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3074 [(set rGPR:$Rd, (add rGPR:$Ra, (bb_mul rGPR:$Rn, rGPR:$Rm)))]>;
3076 [(set rGPR:$Rd, (add rGPR:$Ra, (bt_mul rGPR:$Rn, rGPR:$Rm)))]>;
3078 [(set rGPR:$Rd, (add rGPR:$Ra, (tb_mul rGPR:$Rn, rGPR:$Rm)))]>;
3080 [(set rGPR:$Rd, (add rGPR:$Ra, (tt_mul rGPR:$Rn, rGPR:$Rm)))]>;
3082 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwb rGPR:$Rn, rGPR:$Rm)))]>;
3084 [(set rGPR:$Rd, (add rGPR:$Ra, (ARMsmulwt rGPR:$Rn, rGPR:$Rm)))]>;
3133 (outs rGPR:$Rd),
3135 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm",
3136 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm))]>,
3151 (outs rGPR:$Rd),
3153 IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra",
3154 [(set rGPR:$Rd, (intrinsic rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
3164 (outs rGPR:$Ra, rGPR:$Rd),
3166 IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>,
3167 RegConstraint<"$Ra = $RLo, $Rd = $RHi">,
3189 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
3190 "sdiv", "\t$Rd, $Rn, $Rm",
3191 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
3201 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iDIV,
3202 "udiv", "\t$Rd, $Rn, $Rm",
3203 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
3229 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3230 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>,
3233 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3234 "rbit", "\t$Rd, $Rm",
3235 [(set rGPR:$Rd, (bitreverse rGPR:$Rm))]>,
3238 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3239 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>,
3242 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3243 "rev16", ".w\t$Rd, $Rm",
3244 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>,
3247 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3248 "revsh", ".w\t$Rd, $Rm",
3249 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>,
3257 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh),
3258 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
3259 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
3286 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh),
3287 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
3288 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
3328 : T2ThreeRegNoP<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), NoItinerary,
3329 !strconcat("crc32", suffix, "\t$Rd, $Rn, $Rm"),
3330 [(set rGPR:$Rd, (builtin rGPR:$Rn, rGPR:$Rm))]>,
3372 let Inst{11-8} = 0b1111; // Rd
3385 let Inst{11-8} = 0b1111; // Rd
3400 let Inst{11-8} = 0b1111; // Rd
3429 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
3432 [(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm,
3434 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3438 : t2PseudoInst<(outs rGPR:$Rd),
3441 [(set rGPR:$Rd, (ARMcmov rGPR:$false,t2_so_imm:$imm,
3443 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3448 : t2PseudoInst<(outs rGPR:$Rd),
3451 [(set rGPR:$Rd, (ARMcmov rGPR:$false, imm0_65535:$imm,
3453 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3457 : t2PseudoInst<(outs rGPR:$Rd),
3460 [(set rGPR:$Rd,
3463 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3466 : t2PseudoInst<(outs rGPR:$Rd),
3469 [(set rGPR:$Rd, (ARMcmov rGPR:$false,
3472 RegConstraint<"$false = $Rd">, Sched<[WriteALU]>;
3560 bits<4> Rd;
3563 let Inst{3-0} = Rd;
3641 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
3642 def t2STREXB : T2I_strex<0b0100, (outs rGPR:$Rd),
3645 "strexb", "\t$Rd, $Rt, $addr", "",
3646 [(set rGPR:$Rd,
3649 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
3652 "strexh", "\t$Rd, $Rt, $addr", "",
3653 [(set rGPR:$Rd,
3657 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3660 "strex", "\t$Rd, $Rt, $addr", "",
3661 [(set rGPR:$Rd,
3664 bits<4> Rd;
3671 let Inst{11-8} = Rd;
3675 def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
3678 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3684 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
3687 "stlexb", "\t$Rd, $Rt, $addr", "",
3688 [(set rGPR:$Rd,
3693 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
3696 "stlexh", "\t$Rd, $Rt, $addr", "",
3697 [(set rGPR:$Rd,
3702 def t2STLEX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
3705 "stlex", "\t$Rd, $Rt, $addr", "",
3706 [(set rGPR:$Rd,
3710 bits<4> Rd;
3718 let Inst{3-0} = Rd;
3721 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
3724 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
4331 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr",
4333 bits<4> Rd;
4335 let Inst{11-8} = Rd;
4339 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>;
4341 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr",
4343 bits<4> Rd;
4345 let Inst{11-8} = Rd;
4349 def t2MRSbanked : T2I<(outs rGPR:$Rd), (ins banked_reg:$banked),
4350 NoItinerary, "mrs", "\t$Rd, $banked", []>,
4353 bits<4> Rd;
4359 let Inst{11-8} = Rd;
4370 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$SYSm), NoItinerary,
4371 "mrs", "\t$Rd, $SYSm", []>,
4373 bits<4> Rd;
4376 let Inst{11-8} = Rd;
4766 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
4767 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4768 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
4769 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4773 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
4774 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4775 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
4776 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
4780 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4781 (t2ADDri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p,
4783 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4784 (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4785 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm",
4786 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4787 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm",
4788 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4804 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4805 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4807 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4808 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4815 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4816 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm, pred:$p,
4818 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4819 (t2SUBri12 rGPR:$Rd, rGPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4828 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4829 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4830 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4831 (t2SUBri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
4832 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm",
4833 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
4834 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm",
4835 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm,
4854 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
4855 (t2ADDspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p,
4857 def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
4858 (t2ADDspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;
4873 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
4874 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,
4876 def : t2InstSubst<"add${p} $Rd, $Rn, $imm",
4877 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4884 def : t2InstSubst<"add${s}${p}.w $Rd, $Rn, $imm",
4885 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm, pred:$p,
4887 def : t2InstSubst<"addw${p} $Rd, $Rn, $imm",
4888 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095_neg:$imm, pred:$p)>;
4897 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm",
4898 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4899 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm",
4900 (t2SUBspImm12 GPRsp:$Rd, GPRsp:$Rn, imm0_4095:$imm, pred:$p)>;
4974 def : t2InstAlias<"mvn${s}${p}.w $Rd, $imm",
4975 (t2MVNi rGPR:$Rd, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
4976 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm",
4977 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>;
4978 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm",
4979 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>;
4983 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
4984 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
4986 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
4987 (t2PKHBT rGPR:$Rd, rGPR:$Rm, rGPR:$Rn, 0, pred:$p), 0>,
5021 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>;
5022 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>;
5023 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>;
5028 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm",
5029 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
5039 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
5040 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
5041 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn",
5042 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>;
5065 def : InstAlias<"sxtab${p} $Rd, $Rn, $Rm",
5066 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5068 def : InstAlias<"sxtah${p} $Rd, $Rn, $Rm",
5069 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5071 def : InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
5072 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5074 def : InstAlias<"sxtb16${p} $Rd, $Rm",
5075 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
5078 def : t2InstAlias<"sxtb${p} $Rd, $Rm",
5079 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5080 def : t2InstAlias<"sxth${p} $Rd, $Rm",
5081 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5082 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm",
5083 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5084 def : t2InstAlias<"sxth${p}.w $Rd, $Rm",
5085 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5087 def : InstAlias<"uxtab${p} $Rd, $Rn, $Rm",
5088 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5090 def : InstAlias<"uxtah${p} $Rd, $Rn, $Rm",
5091 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5093 def : InstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
5094 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p), 0>,
5096 def : InstAlias<"uxtb16${p} $Rd, $Rm",
5097 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p), 0>,
5100 def : t2InstAlias<"uxtb${p} $Rd, $Rm",
5101 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5102 def : t2InstAlias<"uxth${p} $Rd, $Rm",
5103 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5104 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm",
5105 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5106 def : t2InstAlias<"uxth${p}.w $Rd, $Rm",
5107 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
5110 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot",
5111 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5112 def : InstAlias<"uxtb16${p} $Rd, $Rm$rot",
5113 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
5115 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot",
5116 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5118 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
5119 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5120 def : InstAlias<"sxtb16${p} $Rd, $Rm$rot",
5121 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p), 0>,
5123 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
5124 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
5127 // "mov Rd, t2_so_imm_not" can be handled via "mvn" in assembly, just like
5129 def : t2InstSubst<"mov${p} $Rd, $imm",
5130 (t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
5131 def : t2InstSubst<"mvn${s}${p} $Rd, $imm",
5132 (t2MOVi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, s_cc_out:$s)>;
5134 def : t2InstSubst<"bic${s}${p} $Rd, $Rn, $imm",
5135 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5140 def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
5141 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5146 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
5147 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5152 def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
5153 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5159 def : t2InstSubst<"orn${s}${p} $Rd, $Rn, $imm",
5160 (t2ORRri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5165 def : t2InstSubst<"orr${s}${p} $Rd, $Rn, $imm",
5166 (t2ORNri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
5171 // Likewise, "add Rd, t2_so_imm_neg" -> sub
5172 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
5173 (t2SUBri rGPR:$Rd, GPRnopc:$Rn, t2_so_imm_neg:$imm,
5175 def : t2InstSubst<"add${s}${p} $Rd, $Rn, $imm",
5176 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rn, t2_so_imm_neg:$imm,
5178 def : t2InstSubst<"add${s}${p} $Rd, $imm",
5179 (t2SUBri rGPR:$Rd, rGPR:$Rd, t2_so_imm_neg:$imm,
5181 def : t2InstSubst<"add${s}${p} $Rd, $imm",
5182 (t2SUBspImm GPRsp:$Rd, GPRsp:$Rd, t2_so_imm_neg:$imm,
5185 def : t2InstSubst<"cmp${p} $Rd, $imm",
5186 (t2CMNri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
5187 def : t2InstSubst<"cmn${p} $Rd, $imm",
5188 (t2CMPri rGPR:$Rd, t2_so_imm_neg:$imm, pred:$p)>;
5196 def : t2InstAlias<"neg${s}${p} $Rd, $Rm",
5197 (t2RSBri rGPR:$Rd, rGPR:$Rm, 0, pred:$p, cc_out:$s)>;
5203 def t2MOVsi: t2AsmPseudo<"mov${p} $Rd, $shift",
5204 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5205 def t2MOVSsi: t2AsmPseudo<"movs${p} $Rd, $shift",
5206 (ins rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5208 def t2MOVsr: t2AsmPseudo<"mov${p} $Rd, $shift",
5209 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5210 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
5211 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5214 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5215 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5216 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5217 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
5218 def : t2InstAlias<"mov${p}.w $Rd, $shift",
5219 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5220 def : t2InstAlias<"movs${p}.w $Rd, $shift",
5221 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
5224 def : t2InstAlias<"adr${p} $Rd, $addr",
5225 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
5250 def : t2InstAlias<"add${p} $Rd, pc, $imm",
5251 (t2ADR rGPR:$Rd, imm0_4095:$imm, pred:$p)>;
5458 : V8_1MI<(outs rGPR:$Rd), (ins GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rm, pred_noal:$fcond),
5459 AddrModeNone, NoItinerary, iname, "$Rd, $Rn, $Rm, $fcond", "", pattern> {
5460 bits<4> Rd;
5468 let Inst{11-8} = Rd{3-0};
5503 def : InstAlias<"csetm\t$Rd, $fcond",
5504 (t2CSINV rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5506 def : InstAlias<"cset\t$Rd, $fcond",
5507 (t2CSINC rGPR:$Rd, ZR, ZR, pred_noal_inv:$fcond)>;
5509 def : InstAlias<"cinc\t$Rd, $Rn, $fcond",
5510 (t2CSINC rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5512 def : InstAlias<"cinv\t$Rd, $Rn, $fcond",
5513 (t2CSINV rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;
5515 def : InstAlias<"cneg\t$Rd, $Rn, $fcond",
5516 (t2CSNEG rGPR:$Rd, GPRwithZRnosp:$Rn, GPRwithZRnosp:$Rn, pred_noal_inv:$fcond)>;