Lines Matching refs:Dm
405 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
406 IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
407 [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>,
430 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
431 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
432 [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>,
455 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
456 IIC_fpDIV64, "vdiv", ".f64\t$Dd, $Dn, $Dm",
457 [(set DPR:$Dd, (fdiv DPR:$Dn, (f64 DPR:$Dm)))]>,
476 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
477 IIC_fpMUL64, "vmul", ".f64\t$Dd, $Dn, $Dm",
478 [(set DPR:$Dd, (fmul DPR:$Dn, (f64 DPR:$Dm)))]>,
500 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
501 IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
502 [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>,
537 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
538 NoItinerary, !strconcat("vsel", op, ".f64\t$Dd, $Dn, $Dm"),
539 [(set DPR:$Dd, (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC))]>,
566 (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
567 NoItinerary, !strconcat(op, ".f64\t$Dd, $Dn, $Dm"),
568 [(set DPR:$Dd, (f64 (SD (f64 DPR:$Dn), (f64 DPR:$Dm))))]>,
586 (outs), (ins DPR:$Dd, DPR:$Dm),
587 IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm",
588 [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>;
605 (outs), (ins DPR:$Dd, DPR:$Dm),
606 IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
607 [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
629 (outs DPR:$Dd), (ins DPR:$Dm),
630 IIC_fpUNA64, "vabs", ".f64\t$Dd, $Dm",
631 [(set DPR:$Dd, (fabs (f64 DPR:$Dm)))]>;
725 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
726 IIC_fpCVTSD, "vcvt", ".f32.f64\t$Sd, $Dm",
727 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
731 bits<5> Dm;
734 let Inst{3-0} = Dm{3-0};
735 let Inst{5} = Dm{4};
832 (outs SPR:$Sd), (ins DPR:$Dm),
833 NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
838 bits<5> Dm;
841 let Inst{3-0} = Dm{3-0};
842 let Inst{5} = Dm{4};
849 def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
850 (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>,
871 (outs SPR:$Sd), (ins DPR:$Dm),
872 NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm",
876 bits<5> Dm;
881 let Inst{3-0} = Dm{3-0};
882 let Inst{5} = Dm{4};
923 (outs SPR:$Sd), (ins DPR:$Dm),
924 NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
927 bits<5> Dm;
932 let Inst{3-0} = Dm{3-0};
933 let Inst{5} = Dm{4};
938 (outs SPR:$Sd), (ins DPR:$Dm),
939 NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
942 bits<5> Dm;
947 let Inst{3-0} = Dm{3-0};
948 let Inst{5} = Dm{4};
992 (outs DPR:$Dd), (ins DPR:$Dm),
993 IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
994 [(set DPR:$Dd, (fneg (f64 DPR:$Dm)))]>;
1029 (outs DPR:$Dd), (ins DPR:$Dm),
1030 NoItinerary, !strconcat("vrint", opc), ".f64\t$Dd, $Dm",
1031 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1043 def : InstAlias<!strconcat("vrint", opc, "$p.f64.f64\t$Dd, $Dm"),
1044 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm, pred:$p), 0>,
1071 (outs DPR:$Dd), (ins DPR:$Dm),
1072 NoItinerary, !strconcat("vrint", opc, ".f64\t$Dd, $Dm"),
1073 [(set (f64 DPR:$Dd), (node (f64 DPR:$Dm)))]>,
1082 def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
1083 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
1093 (outs DPR:$Dd), (ins DPR:$Dm),
1094 IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
1095 [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>,
1112 (outs DPR:$Dd), (ins DPR:$Dm),
1113 IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>,
1191 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1192 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1193 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
1197 bits<5> Dm;
1202 let Inst{3-0} = Dm{3-0};
1203 let Inst{5} = Dm{4};
1214 // $Rt = EXTRACT_SUBREG $Dm, ssub_0
1215 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1248 (outs DPR:$Dm), (ins GPR:$Rt, GPR:$Rt2),
1249 IIC_fpMOVID, "vmov", "\t$Dm, $Rt, $Rt2",
1250 [(set DPR:$Dm, (arm_fmdrr GPR:$Rt, GPR:$Rt2))]>,
1254 bits<5> Dm;
1259 let Inst{3-0} = Dm{3-0};
1260 let Inst{5} = Dm{4};
1271 // $Dm = REG_SEQUENCE $Rt, ssub_0, $Rt2, ssub_1
1537 bits<5> Dm;
1540 let Inst{3-0} = Dm{3-0};
1541 let Inst{5} = Dm{4};
1590 (outs SPR:$Sd), (ins DPR:$Dm),
1591 IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
1637 (outs SPR:$Sd), (ins DPR:$Dm),
1638 IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
1686 (outs SPR:$Sd), (ins DPR:$Dm),
1687 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1688 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1711 (outs SPR:$Sd), (ins DPR:$Dm),
1712 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1713 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1738 (outs SPR:$Sd), (ins DPR:$Dm),
1739 IIC_fpCVTDI, "vjcvt", ".s32.f64\t$Sd, $Dm",
1991 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
1992 IIC_fpMAC64, "vmla", ".f64\t$Dd, $Dn, $Dm",
1993 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2032 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2033 IIC_fpMAC64, "vmls", ".f64\t$Dd, $Dn, $Dm",
2034 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2072 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2073 IIC_fpMAC64, "vnmla", ".f64\t$Dd, $Dn, $Dm",
2074 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2124 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2125 IIC_fpMAC64, "vnmls", ".f64\t$Dd, $Dn, $Dm",
2126 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2165 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2166 IIC_fpFMAC64, "vfma", ".f64\t$Dd, $Dn, $Dm",
2167 [(set DPR:$Dd, (fadd_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2206 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, DPR:$Ddin)),
2207 (VFMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2217 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2218 IIC_fpFMAC64, "vfms", ".f64\t$Dd, $Dn, $Dm",
2219 [(set DPR:$Dd, (fadd_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2258 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin)),
2259 (VFMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2269 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2270 IIC_fpFMAC64, "vfnma", ".f64\t$Dd, $Dn, $Dm",
2271 [(set DPR:$Dd,(fsub_mlx (fneg (fmul_su DPR:$Dn,DPR:$Dm)),
2307 def : Pat<(fneg (fma (f64 DPR:$Dn), (f64 DPR:$Dm), (f64 DPR:$Ddin))),
2308 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2317 def : Pat<(f64 (fma (fneg DPR:$Dn), DPR:$Dm, (fneg DPR:$Ddin))),
2318 (VFNMAD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2328 (outs DPR:$Dd), (ins DPR:$Ddin, DPR:$Dn, DPR:$Dm),
2329 IIC_fpFMAC64, "vfnms", ".f64\t$Dd, $Dn, $Dm",
2330 [(set DPR:$Dd, (fsub_mlx (fmul_su DPR:$Dn, DPR:$Dm),
2365 def : Pat<(f64 (fma DPR:$Dn, DPR:$Dm, (fneg DPR:$Ddin))),
2366 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2375 def : Pat<(fneg (f64 (fma (fneg DPR:$Dn), DPR:$Dm, DPR:$Ddin))),
2376 (VFNMSD DPR:$Ddin, DPR:$Dn, DPR:$Dm)>,
2390 def VMOVDcc : PseudoInst<(outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm, cmovpred:$p),
2393 (ARMcmov DPR:$Dn, DPR:$Dm, cmovpred:$p))]>,
2689 def : VFP2DPInstAlias<"faddd${p} $Dd, $Dn, $Dm",
2690 (VADDD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2693 def : VFP2DPInstAlias<"fsubd${p} $Dd, $Dn, $Dm",
2694 (VSUBD DPR:$Dd, DPR:$Dn, DPR:$Dm, pred:$p)>;
2698 def : VFP2DPInstAlias<"vsqrt${p} $Dd, $Dm", (VSQRTD DPR:$Dd, DPR:$Dm, pred:$p)>;