Lines Matching refs:SPR
159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
412 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
414 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
437 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
439 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
462 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
464 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
483 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
485 [(set SPR:$Sd, (fmul SPR:$Sn, SPR:$Sm))]>,
506 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
508 [(set SPR:$Sd, (fneg (fmul SPR:$Sn, SPR:$Sm)))]>,
531 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
533 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC))]>,
560 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
562 [(set SPR:$Sd, (SD SPR:$Sn, SPR:$Sm))]>,
580 def : Pat<(fmul (fneg SPR:$a), SPR:$b),
581 (VNMULS SPR:$a, SPR:$b)>, Requires<[NoHonorSignDependentRounding]>;
591 (outs), (ins SPR:$Sd, SPR:$Sm),
593 [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
610 (outs), (ins SPR:$Sd, SPR:$Sm),
612 [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
634 (outs SPR:$Sd), (ins SPR:$Sm),
636 [(set SPR:$Sd, (fabs SPR:$Sm))]> {
657 (outs), (ins SPR:$Sd),
659 [(arm_cmpfpe0 SPR:$Sd)]> {
685 (outs), (ins SPR:$Sd),
687 [(arm_cmpfp0 SPR:$Sd)]> {
706 (outs DPR:$Dd), (ins SPR:$Sm),
708 [(set DPR:$Dd, (fpextend SPR:$Sm))]>,
725 def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
727 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
751 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
758 (VCVTBHS (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>;
760 (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
763 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
769 def : FP16Pat<(f16 (fpround SPR:$Sm)),
770 (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>;
771 def : FP16Pat<(fp_to_f16 SPR:$a),
772 (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
773 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
774 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTBSH SPR:$src2),
776 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_even:$lane),
777 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTBSH SPR:$src2),
781 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
795 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
801 def : FP16Pat<(insertelt (v8f16 MQPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
802 (v8f16 (INSERT_SUBREG (v8f16 MQPR:$src1), (VCVTTSH SPR:$src2),
804 def : FP16Pat<(insertelt (v4f16 DPR:$src1), (f16 (fpround (f32 SPR:$src2))), imm_odd:$lane),
805 (v4f16 (INSERT_SUBREG (v4f16 DPR:$src1), (VCVTTSH SPR:$src2),
809 (outs DPR:$Dd), (ins SPR:$Sm),
825 (VCVTBHD (COPY_TO_REGCLASS (f16 HPR:$Sm), SPR))>,
828 (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
832 (outs SPR:$Sd), (ins DPR:$Dm),
857 (outs DPR:$Dd), (ins SPR:$Sm),
871 (outs SPR:$Sd), (ins DPR:$Dm),
891 (outs SPR:$Sd), (ins HPR:$Sm),
899 (outs SPR:$Sd), (ins HPR:$Sm),
907 (outs SPR:$Sd), (ins SPR:$Sm),
915 (outs SPR:$Sd), (ins SPR:$Sm),
923 (outs SPR:$Sd), (ins DPR:$Dm),
938 (outs SPR:$Sd), (ins DPR:$Dm),
965 def : Pat<(i32 (fp_to_sint (node SPR:$a))),
967 (!cast<Instruction>(NAME#"SS") SPR:$a),
969 def : Pat<(i32 (fp_to_uint (node SPR:$a))),
971 (!cast<Instruction>(NAME#"US") SPR:$a),
997 (outs SPR:$Sd), (ins SPR:$Sm),
999 [(set SPR:$Sd, (fneg SPR:$Sm))]> {
1021 (outs SPR:$Sd), (ins SPR:$Sm),
1023 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1038 (!cast<Instruction>(NAME#"H") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1041 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm, pred:$p), 0>,
1064 (outs SPR:$Sd), (ins SPR:$Sm),
1066 [(set (f32 SPR:$Sd), (node (f32 SPR:$Sm)))]>,
1080 (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
1099 (outs SPR:$Sd), (ins SPR:$Sm),
1101 [(set SPR:$Sd, (fsqrt SPR:$Sm))]>,
1117 (outs SPR:$Sd), (ins SPR:$Sm),
1124 (outs SPR:$Sd), (ins SPR:$Sm),
1129 (outs SPR:$Sd), (ins SPR:$Sm),
1141 (outs GPR:$Rt), (ins SPR:$Sn),
1143 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1165 (outs SPR:$Sn), (ins GPR:$Rt),
1167 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1220 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1244 // FMDHR: GPR -> SPR
1245 // FMDLR: GPR -> SPR
1293 (outs SPR:$dst1, SPR:$dst2), (ins GPR:$src1, GPR:$src2),
1367 // FMRDH: SPR -> GPR
1368 // FMRDL: SPR -> GPR
1369 // FMRRS: SPR -> GPR
1370 // FMRX: SPR system reg -> GPR
1371 // FMSRR: GPR -> SPR
1436 (outs DPR:$Dd), (ins SPR:$Sm),
1445 (VSITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1452 (outs SPR:$Sd),(ins SPR:$Sm),
1464 (VSITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1470 (outs HPR:$Sd), (ins SPR:$Sm),
1479 (VSITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
1482 (outs DPR:$Dd), (ins SPR:$Sm),
1491 (VUITOD (COPY_TO_REGCLASS GPR:$a, SPR))>;
1498 (outs SPR:$Sd), (ins SPR:$Sm),
1510 (VUITOS (COPY_TO_REGCLASS GPR:$a, SPR))>;
1516 (outs HPR:$Sd), (ins SPR:$Sm),
1525 (VUITOH (COPY_TO_REGCLASS GPR:$a, SPR))>;
1590 (outs SPR:$Sd), (ins DPR:$Dm),
1606 (outs SPR:$Sd), (ins SPR:$Sm),
1617 def : VFPNoNEONPat<(i32 (fp_to_sint SPR:$a)),
1618 (COPY_TO_REGCLASS (VTOSIZS SPR:$a), GPR)>;
1620 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_sint (f32 SPR:$a))),
1622 (VSTRS (VTOSIZS SPR:$a), addrmode5:$ptr)>;
1625 (outs SPR:$Sd), (ins HPR:$Sm),
1637 (outs SPR:$Sd), (ins DPR:$Dm),
1653 (outs SPR:$Sd), (ins SPR:$Sm),
1664 def : VFPNoNEONPat<(i32 (fp_to_uint SPR:$a)),
1665 (COPY_TO_REGCLASS (VTOUIZS SPR:$a), GPR)>;
1667 def : VFPNoNEONPat<(alignedstore32 (i32 (fp_to_uint (f32 SPR:$a))),
1669 (VSTRS (VTOUIZS SPR:$a), addrmode5:$ptr)>;
1672 (outs SPR:$Sd), (ins HPR:$Sm),
1686 (outs SPR:$Sd), (ins DPR:$Dm),
1688 [(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>,
1694 (outs SPR:$Sd), (ins SPR:$Sm),
1696 [(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]>,
1702 (outs SPR:$Sd), (ins SPR:$Sm),
1711 (outs SPR:$Sd), (ins DPR:$Dm),
1713 [(set SPR:$Sd, (int_arm_vcvtru(f64 DPR:$Dm)))]>,
1719 (outs SPR:$Sd), (ins SPR:$Sm),
1721 [(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]>,
1727 (outs SPR:$Sd), (ins SPR:$Sm),
1738 (outs SPR:$Sd), (ins DPR:$Dm),
1786 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1792 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1798 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1804 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1812 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1821 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1830 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1839 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1872 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1878 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1884 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1890 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1898 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1907 (outs SPR:$dst), (ins SPR:$a, fbits16:$fbits),
1916 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1925 (outs SPR:$dst), (ins SPR:$a, fbits32:$fbits),
1957 : VFPAI<(outs SPR:$Sd), (ins SPR:$dst, SPR:$Sm),
2000 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2002 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2003 SPR:$Sdin))]>,
2023 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2024 (VMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2041 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2043 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2044 SPR:$Sdin))]>,
2064 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2065 (VMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2081 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2083 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2084 SPR:$Sdin))]>,
2105 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
2106 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2116 def : Pat<(fsub_mlx (fneg SPR:$dstin), (fmul_su SPR:$a, SPR:$b)),
2117 (VNMLAS SPR:$dstin, SPR:$a, SPR:$b)>,
2133 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2135 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2154 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2155 (VNMLSS SPR:$dstin, SPR:$a, SPR:$b)>,
2174 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2176 [(set SPR:$Sd, (fadd_mlx (fmul_su SPR:$Sn, SPR:$Sm),
2177 SPR:$Sdin))]>,
2197 def : Pat<(fadd_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2198 (VFMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2209 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, SPR:$Sdin)),
2210 (VFMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2226 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2228 [(set SPR:$Sd, (fadd_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2229 SPR:$Sdin))]>,
2249 def : Pat<(fsub_mlx SPR:$dstin, (fmul_su SPR:$a, SPR:$b)),
2250 (VFMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2261 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin)),
2262 (VFMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2278 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2280 [(set SPR:$Sd, (fsub_mlx (fneg (fmul_su SPR:$Sn, SPR:$Sm)),
2281 SPR:$Sdin))]>,
2301 def : Pat<(fsub_mlx (fneg (fmul_su SPR:$a, SPR:$b)), SPR:$dstin),
2302 (VFNMAS SPR:$dstin, SPR:$a, SPR:$b)>,
2310 def : Pat<(fneg (fma (f32 SPR:$Sn), (f32 SPR:$Sm), (f32 SPR:$Sdin))),
2311 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2320 def : Pat<(f32 (fma (fneg SPR:$Sn), SPR:$Sm, (fneg SPR:$Sdin))),
2321 (VFNMAS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2337 (outs SPR:$Sd), (ins SPR:$Sdin, SPR:$Sn, SPR:$Sm),
2339 [(set SPR:$Sd, (fsub_mlx (fmul_su SPR:$Sn, SPR:$Sm), SPR:$Sdin))]>,
2358 def : Pat<(fsub_mlx (fmul_su SPR:$a, SPR:$b), SPR:$dstin),
2359 (VFNMSS SPR:$dstin, SPR:$a, SPR:$b)>,
2368 def : Pat<(f32 (fma SPR:$Sn, SPR:$Sm, (fneg SPR:$Sdin))),
2369 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2378 def : Pat<(fneg (f32 (fma (fneg SPR:$Sn), SPR:$Sm, SPR:$Sdin))),
2379 (VFNMSS SPR:$Sdin, SPR:$Sn, SPR:$Sm)>,
2396 def VMOVScc : PseudoInst<(outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm, cmovpred:$p),
2398 [(set (f32 SPR:$Sd),
2399 (ARMcmov SPR:$Sn, SPR:$Sm, cmovpred:$p))]>,
2590 def FCONSTS : VFPAI<(outs SPR:$Sd), (ins vfp_f32imm:$imm),
2593 [(set SPR:$Sd, vfp_f32imm:$imm)]>, Requires<[HasVFP3]> {
2630 (f32 (COPY_TO_REGCLASS (f16 (FCONSTH (vfp_f32f16imm_xform (f32 $imm)))), SPR))> {
2683 def : VFP2InstAlias<"fcmpzs${p} $val", (VCMPZS SPR:$val, pred:$p)>;
2688 (VADDS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2692 (VSUBS SPR:$Sd, SPR:$Sn, SPR:$Sm, pred:$p)>;
2697 def : VFP2InstAlias<"vsqrt${p} $Sd, $Sm", (VSQRTS SPR:$Sd, SPR:$Sm, pred:$p)>;
2702 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2704 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
2712 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2714 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2716 (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>;
2718 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2720 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2722 (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>;
2732 (VMOVS SPR:$Sd, SPR:$Sm, pred:$p)>;
2743 (FCONSTS SPR:$Sd, vfp_f32imm:$val, pred:$p)>;