Lines Matching refs:F0
102 def A57UnitW : ProcResource<1>; // Type W micro-ops (F0)
724 // fp compare - 3cyc F1 for unconditional, 6cyc "F0/F1, F1" for conditional
765 // FP multiply accumulate, FZ: 9cyc "F0/F1" or 4 cyc for sequenced accumulate
795 // VMOV: 3cyc "F0/F1" for imm/reg
807 // 8cyc "L,F0/F1" for FP transfer, core reg to upper or lower half of vfp D-reg
971 // ASIMD absolute diff, 3cyc F0/F1 for integer VABD
989 // ASIMD absolute diff long: 3cyc F0/F1 for VABDL
1014 // ASIMD multiply, D-form: 5cyc F0 for r0px, 4cyc F0 for r1p0 and later
1024 // ASIMD multiply, Q-form: 6cyc F0 for r0px, 5cyc F0 for r1p0 and later
1033 // 5cyc F0 for r0px, 4cyc F0 for r1p0 and later, 1cyc for accumulate sequence
1046 // 6cyc F0 for r0px, 5cyc F0 for r1p0 and later, 2cyc for accumulate sequence
1059 // 5cyc F0 for r0px, 4cyc F0 for r1p0 and later, 1cyc for accumulate sequence
1072 // 5cyc F0 for r0px, 4cyc F0 for r1p0 and later, 2cyc for accumulate sequence
1090 // 5cyc F0 for r0px, 4cyc F0 for r1p0 and later
1165 // ASIMD FP convert, half-precision: 8cyc F0/F1
1180 // ASIMD FP multiply accumulate: 9cyc F0/F1, 4cyc for accumulate sequence
1202 // ASIMD duplicate, core reg: 8cyc "L, F0/F1"
1205 // ASIMD duplicate, scalar: 3cyc "F0/F1"
1237 // ASIMD transfer, core reg to scalar: 8cyc "L, F0/F1"
1275 // ASIMD load, 1 element, one lane and all lanes: 8cyc "L, F0/F1"
1281 // ASIMD load, 2 element, multiple, 2 reg: 8cyc "L, F0/F1"
1287 // ASIMD load, 2 element, multiple, 4 reg: 9cyc "L, F0/F1"
1292 // ASIMD load, 2 element, one lane and all lanes: 8cyc "L, F0/F1"
1304 // ASIMD load, 3 element, multiple, 3 reg: 9cyc "L, F0/F1"
1319 // ASIMD load, 3 element, one lane, size 32: 8cyc "L, F0/F1"
1329 // ASIMD load, 3 element, one lane, size 8/16: 9cyc "L, F0/F1"
1339 // ASIMD load, 3 element, all lanes: 8cyc "L, F0/F1"
1349 // ASIMD load, 4 element, multiple, 4 reg: 9cyc "L, F0/F1"
1361 // ASIMD load, 4 element, one lane, size 32: 8cyc "L, F0/F1"
1373 // ASIMD load, 4 element, one lane, size 8/16: 9cyc "L, F0/F1"
1385 // ASIMD load, 4 element, all lanes: 8cyc "L, F0/F1"
1417 // ASIMD store, 1 element, one lane: 3cyc "F0/F1, S"
1422 // ASIMD store, 2 element, multiple, 2 reg: 3cyc "F0/F1, S"
1427 // ASIMD store, 2 element, multiple, 4 reg: 4cyc "F0/F1, S"
1432 // ASIMD store, 2 element, one lane: 3cyc "F0/F1, S"
1465 // AESD, AESE, AESIMC, AESMC: 3cyc F0
1467 // Crypto polynomial (64x64) multiply long (VMULL.P64): 3cyc F0
1469 // Crypto SHA1 xor ops: 6cyc F0/F1
1471 // Crypto SHA1 fast ops: 3cyc F0
1473 // Crypto SHA1 slow ops: 6cyc F0
1475 // Crypto SHA256 fast ops: 3cyc F0
1477 // Crypto SHA256 slow ops: 6cyc F0