136     Register DestReg = MI.getOperand(0).getReg();  in optimizeSelect()  local
138     if (!DestReg.isVirtual())  in optimizeSelect()
142                                         get(ARM::t2CSEL), DestReg)  in optimizeSelect()
154                                   const DebugLoc &DL, MCRegister DestReg,  in copyPhysReg()  argument
157   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
158     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);  in copyPhysReg()
160   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
210                      Register DestReg, int FI,  in loadRegFromStackSlot()  argument
222     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)  in loadRegFromStackSlot()
234     if (Register::isVirtualRegister(DestReg)) {  in loadRegFromStackSlot()
236       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);  in loadRegFromStackSlot()
240     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
241     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
244     if (Register::isPhysicalRegister(DestReg))  in loadRegFromStackSlot()
245       MIB.addReg(DestReg, RegState::ImplicitDefine);  in loadRegFromStackSlot()
249   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);  in loadRegFromStackSlot()
279                                   const DebugLoc &dl, Register DestReg,  in emitT2RegPlusImmediate()  argument
284   if (NumBytes == 0 && DestReg != BaseReg) {  in emitT2RegPlusImmediate()
285     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
296   if (DestReg != ARM::SP && DestReg != BaseReg &&  in emitT2RegPlusImmediate()
302       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)  in emitT2RegPlusImmediate()
308       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)  in emitT2RegPlusImmediate()
309         .addReg(DestReg)  in emitT2RegPlusImmediate()
317         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)  in emitT2RegPlusImmediate()
319             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
329         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)  in emitT2RegPlusImmediate()
331             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
343     if (DestReg == ARM::SP && BaseReg != ARM::SP) {  in emitT2RegPlusImmediate()
345       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
353     assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&  in emitT2RegPlusImmediate()
357     if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {  in emitT2RegPlusImmediate()
360       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
369     bool ToSP = DestReg == ARM::SP;  in emitT2RegPlusImmediate()
395     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
403     BaseReg = DestReg;  in emitT2RegPlusImmediate()