66                                     unsigned MIFlags) {  in emitThumb1LoadConstPool()  argument
78     .setMIFlags(MIFlags);  in emitThumb1LoadConstPool()
86                                     unsigned MIFlags) {  in emitThumb2LoadConstPool()  argument
98       .setMIFlags(MIFlags);  in emitThumb2LoadConstPool()
106     ARMCC::CondCodes Pred, Register PredReg, unsigned MIFlags) const {  in emitLoadConstPool()
113                                    PredReg, MIFlags);  in emitLoadConstPool()
116                                  PredReg, MIFlags);  in emitLoadConstPool()
127     const ARMBaseRegisterInfo &MRI, unsigned MIFlags = MachineInstr::NoFlags) {  in emitThumbRegPlusImmInReg()  argument
151         .setMIFlags(MIFlags);  in emitThumbRegPlusImmInReg()
156         .setMIFlags(MIFlags);  in emitThumbRegPlusImmInReg()
160         .setMIFlags(MIFlags);  in emitThumbRegPlusImmInReg()
163       .addImm(NumBytes).setMIFlags(MIFlags);  in emitThumbRegPlusImmInReg()
166                           MIFlags);  in emitThumbRegPlusImmInReg()
191                                      unsigned MIFlags) {  in emitThumbRegPlusImmediate()  argument
302                              TII, MRI, MIFlags);  in emitThumbRegPlusImmediate()
318     MIB.setMIFlags(MIFlags).add(predOps(ARMCC::AL));  in emitThumbRegPlusImmediate()
334        .setMIFlags(MIFlags);  in emitThumbRegPlusImmediate()