Lines Matching refs:Hexagon
68 assert(Hexagon::IntRegsRegClass.contains(Reg)); in getHexagonRegisterPair()
71 assert(Hexagon::DoubleRegsRegClass.contains(Pair)); in getHexagonRegisterPair()
135 if (Hexagon::DoubleRegsRegClass.contains(RegNumber)) in PrintAsmOperand()
137 Hexagon::isub_lo : in PrintAsmOperand()
138 Hexagon::isub_hi); in PrintAsmOperand()
271 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; in HexagonProcessInstruction()
277 case Hexagon::A2_iconst: { in HexagonProcessInstruction()
278 Inst.setOpcode(Hexagon::A2_addi); in HexagonProcessInstruction()
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0)); in HexagonProcessInstruction()
290 case Hexagon::A2_tfrf: { in HexagonProcessInstruction()
292 Inst.setOpcode(Hexagon::A2_paddif); in HexagonProcessInstruction()
297 case Hexagon::A2_tfrt: { in HexagonProcessInstruction()
299 Inst.setOpcode(Hexagon::A2_paddit); in HexagonProcessInstruction()
304 case Hexagon::A2_tfrfnew: { in HexagonProcessInstruction()
306 Inst.setOpcode(Hexagon::A2_paddifnew); in HexagonProcessInstruction()
311 case Hexagon::A2_tfrtnew: { in HexagonProcessInstruction()
313 Inst.setOpcode(Hexagon::A2_padditnew); in HexagonProcessInstruction()
318 case Hexagon::A2_zxtb: { in HexagonProcessInstruction()
320 Inst.setOpcode(Hexagon::A2_andir); in HexagonProcessInstruction()
326 case Hexagon::CONST64: in HexagonProcessInstruction()
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp); in HexagonProcessInstruction()
344 case Hexagon::CONST32: in HexagonProcessInstruction()
352 TmpInst.setOpcode(Hexagon::L2_loadrigp); in HexagonProcessInstruction()
363 case Hexagon::C2_pxfer_map: { in HexagonProcessInstruction()
365 MappedInst.setOpcode(Hexagon::C2_or); in HexagonProcessInstruction()
373 case Hexagon::M2_vrcmpys_acc_s1: { in HexagonProcessInstruction()
378 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h); in HexagonProcessInstruction()
380 MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l); in HexagonProcessInstruction()
384 case Hexagon::M2_vrcmpys_s1: { in HexagonProcessInstruction()
389 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h); in HexagonProcessInstruction()
391 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l); in HexagonProcessInstruction()
396 case Hexagon::M2_vrcmpys_s1rp: { in HexagonProcessInstruction()
401 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h); in HexagonProcessInstruction()
403 MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l); in HexagonProcessInstruction()
408 case Hexagon::A4_boundscheck: { in HexagonProcessInstruction()
413 MappedInst.setOpcode(Hexagon::A4_boundscheck_hi); in HexagonProcessInstruction()
415 MappedInst.setOpcode(Hexagon::A4_boundscheck_lo); in HexagonProcessInstruction()
420 case Hexagon::PS_call_nr: in HexagonProcessInstruction()
421 Inst.setOpcode(Hexagon::J2_call); in HexagonProcessInstruction()
424 case Hexagon::S5_asrhub_rnd_sat_goodsyntax: { in HexagonProcessInstruction()
433 TmpInst.setOpcode(Hexagon::S2_vsathub); in HexagonProcessInstruction()
439 TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat); in HexagonProcessInstruction()
450 case Hexagon::S5_vasrhrnd_goodsyntax: in HexagonProcessInstruction()
451 case Hexagon::S2_asr_i_p_rnd_goodsyntax: { in HexagonProcessInstruction()
460 TmpInst.setOpcode(Hexagon::A2_combinew); in HexagonProcessInstruction()
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
472 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax) in HexagonProcessInstruction()
473 TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd); in HexagonProcessInstruction()
475 TmpInst.setOpcode(Hexagon::S5_vasrhrnd); in HexagonProcessInstruction()
487 case Hexagon::S2_asr_i_r_rnd_goodsyntax: { in HexagonProcessInstruction()
496 TmpInst.setOpcode(Hexagon::A2_tfr); in HexagonProcessInstruction()
502 TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd); in HexagonProcessInstruction()
514 case Hexagon::A2_tfrpi: { in HexagonProcessInstruction()
519 TmpInst.setOpcode(Hexagon::A2_combineii); in HexagonProcessInstruction()
538 case Hexagon::A2_tfrp: { in HexagonProcessInstruction()
540 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
541 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
545 MappedInst.setOpcode(Hexagon::A2_combinew); in HexagonProcessInstruction()
549 case Hexagon::A2_tfrpt: in HexagonProcessInstruction()
550 case Hexagon::A2_tfrpf: { in HexagonProcessInstruction()
552 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
553 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
557 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt) in HexagonProcessInstruction()
558 ? Hexagon::C2_ccombinewt in HexagonProcessInstruction()
559 : Hexagon::C2_ccombinewf); in HexagonProcessInstruction()
563 case Hexagon::A2_tfrptnew: in HexagonProcessInstruction()
564 case Hexagon::A2_tfrpfnew: { in HexagonProcessInstruction()
566 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
567 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
571 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew in HexagonProcessInstruction()
572 ? Hexagon::C2_ccombinewnewt in HexagonProcessInstruction()
573 : Hexagon::C2_ccombinewnewf); in HexagonProcessInstruction()
577 case Hexagon::M2_mpysmi: { in HexagonProcessInstruction()
585 MappedInst.setOpcode(Hexagon::M2_mpysin); in HexagonProcessInstruction()
589 MappedInst.setOpcode(Hexagon::M2_mpysip); in HexagonProcessInstruction()
593 case Hexagon::A2_addsp: { in HexagonProcessInstruction()
598 MappedInst.setOpcode(Hexagon::A2_addsph); in HexagonProcessInstruction()
600 MappedInst.setOpcode(Hexagon::A2_addspl); in HexagonProcessInstruction()
605 case Hexagon::V6_vd0: { in HexagonProcessInstruction()
610 TmpInst.setOpcode(Hexagon::V6_vxor); in HexagonProcessInstruction()
618 case Hexagon::V6_vdd0: { in HexagonProcessInstruction()
623 TmpInst.setOpcode(Hexagon::V6_vsubw_dv); in HexagonProcessInstruction()
631 case Hexagon::V6_vL32Ub_pi: in HexagonProcessInstruction()
632 case Hexagon::V6_vL32b_cur_pi: in HexagonProcessInstruction()
633 case Hexagon::V6_vL32b_nt_cur_pi: in HexagonProcessInstruction()
634 case Hexagon::V6_vL32b_pi: in HexagonProcessInstruction()
635 case Hexagon::V6_vL32b_nt_pi: in HexagonProcessInstruction()
636 case Hexagon::V6_vL32b_nt_tmp_pi: in HexagonProcessInstruction()
637 case Hexagon::V6_vL32b_tmp_pi: in HexagonProcessInstruction()
641 case Hexagon::V6_vL32Ub_ai: in HexagonProcessInstruction()
642 case Hexagon::V6_vL32b_ai: in HexagonProcessInstruction()
643 case Hexagon::V6_vL32b_cur_ai: in HexagonProcessInstruction()
644 case Hexagon::V6_vL32b_nt_ai: in HexagonProcessInstruction()
645 case Hexagon::V6_vL32b_nt_cur_ai: in HexagonProcessInstruction()
646 case Hexagon::V6_vL32b_nt_tmp_ai: in HexagonProcessInstruction()
647 case Hexagon::V6_vL32b_tmp_ai: in HexagonProcessInstruction()
651 case Hexagon::V6_vS32Ub_pi: in HexagonProcessInstruction()
652 case Hexagon::V6_vS32b_new_pi: in HexagonProcessInstruction()
653 case Hexagon::V6_vS32b_nt_new_pi: in HexagonProcessInstruction()
654 case Hexagon::V6_vS32b_nt_pi: in HexagonProcessInstruction()
655 case Hexagon::V6_vS32b_pi: in HexagonProcessInstruction()
659 case Hexagon::V6_vS32Ub_ai: in HexagonProcessInstruction()
660 case Hexagon::V6_vS32b_ai: in HexagonProcessInstruction()
661 case Hexagon::V6_vS32b_new_ai: in HexagonProcessInstruction()
662 case Hexagon::V6_vS32b_nt_ai: in HexagonProcessInstruction()
663 case Hexagon::V6_vS32b_nt_new_ai: in HexagonProcessInstruction()
667 case Hexagon::V6_vL32b_cur_npred_pi: in HexagonProcessInstruction()
668 case Hexagon::V6_vL32b_cur_pred_pi: in HexagonProcessInstruction()
669 case Hexagon::V6_vL32b_npred_pi: in HexagonProcessInstruction()
670 case Hexagon::V6_vL32b_nt_cur_npred_pi: in HexagonProcessInstruction()
671 case Hexagon::V6_vL32b_nt_cur_pred_pi: in HexagonProcessInstruction()
672 case Hexagon::V6_vL32b_nt_npred_pi: in HexagonProcessInstruction()
673 case Hexagon::V6_vL32b_nt_pred_pi: in HexagonProcessInstruction()
674 case Hexagon::V6_vL32b_nt_tmp_npred_pi: in HexagonProcessInstruction()
675 case Hexagon::V6_vL32b_nt_tmp_pred_pi: in HexagonProcessInstruction()
676 case Hexagon::V6_vL32b_pred_pi: in HexagonProcessInstruction()
677 case Hexagon::V6_vL32b_tmp_npred_pi: in HexagonProcessInstruction()
678 case Hexagon::V6_vL32b_tmp_pred_pi: in HexagonProcessInstruction()
682 case Hexagon::V6_vL32b_cur_npred_ai: in HexagonProcessInstruction()
683 case Hexagon::V6_vL32b_cur_pred_ai: in HexagonProcessInstruction()
684 case Hexagon::V6_vL32b_npred_ai: in HexagonProcessInstruction()
685 case Hexagon::V6_vL32b_nt_cur_npred_ai: in HexagonProcessInstruction()
686 case Hexagon::V6_vL32b_nt_cur_pred_ai: in HexagonProcessInstruction()
687 case Hexagon::V6_vL32b_nt_npred_ai: in HexagonProcessInstruction()
688 case Hexagon::V6_vL32b_nt_pred_ai: in HexagonProcessInstruction()
689 case Hexagon::V6_vL32b_nt_tmp_npred_ai: in HexagonProcessInstruction()
690 case Hexagon::V6_vL32b_nt_tmp_pred_ai: in HexagonProcessInstruction()
691 case Hexagon::V6_vL32b_pred_ai: in HexagonProcessInstruction()
692 case Hexagon::V6_vL32b_tmp_npred_ai: in HexagonProcessInstruction()
693 case Hexagon::V6_vL32b_tmp_pred_ai: in HexagonProcessInstruction()
697 case Hexagon::V6_vS32Ub_npred_pi: in HexagonProcessInstruction()
698 case Hexagon::V6_vS32Ub_pred_pi: in HexagonProcessInstruction()
699 case Hexagon::V6_vS32b_new_npred_pi: in HexagonProcessInstruction()
700 case Hexagon::V6_vS32b_new_pred_pi: in HexagonProcessInstruction()
701 case Hexagon::V6_vS32b_npred_pi: in HexagonProcessInstruction()
702 case Hexagon::V6_vS32b_nqpred_pi: in HexagonProcessInstruction()
703 case Hexagon::V6_vS32b_nt_new_npred_pi: in HexagonProcessInstruction()
704 case Hexagon::V6_vS32b_nt_new_pred_pi: in HexagonProcessInstruction()
705 case Hexagon::V6_vS32b_nt_npred_pi: in HexagonProcessInstruction()
706 case Hexagon::V6_vS32b_nt_nqpred_pi: in HexagonProcessInstruction()
707 case Hexagon::V6_vS32b_nt_pred_pi: in HexagonProcessInstruction()
708 case Hexagon::V6_vS32b_nt_qpred_pi: in HexagonProcessInstruction()
709 case Hexagon::V6_vS32b_pred_pi: in HexagonProcessInstruction()
710 case Hexagon::V6_vS32b_qpred_pi: in HexagonProcessInstruction()
714 case Hexagon::V6_vS32Ub_npred_ai: in HexagonProcessInstruction()
715 case Hexagon::V6_vS32Ub_pred_ai: in HexagonProcessInstruction()
716 case Hexagon::V6_vS32b_new_npred_ai: in HexagonProcessInstruction()
717 case Hexagon::V6_vS32b_new_pred_ai: in HexagonProcessInstruction()
718 case Hexagon::V6_vS32b_npred_ai: in HexagonProcessInstruction()
719 case Hexagon::V6_vS32b_nqpred_ai: in HexagonProcessInstruction()
720 case Hexagon::V6_vS32b_nt_new_npred_ai: in HexagonProcessInstruction()
721 case Hexagon::V6_vS32b_nt_new_pred_ai: in HexagonProcessInstruction()
722 case Hexagon::V6_vS32b_nt_npred_ai: in HexagonProcessInstruction()
723 case Hexagon::V6_vS32b_nt_nqpred_ai: in HexagonProcessInstruction()
724 case Hexagon::V6_vS32b_nt_pred_ai: in HexagonProcessInstruction()
725 case Hexagon::V6_vS32b_nt_qpred_ai: in HexagonProcessInstruction()
726 case Hexagon::V6_vS32b_pred_ai: in HexagonProcessInstruction()
727 case Hexagon::V6_vS32b_qpred_ai: in HexagonProcessInstruction()
732 case Hexagon::V6_vS32b_srls_ai: in HexagonProcessInstruction()
736 case Hexagon::V6_vS32b_srls_pi: in HexagonProcessInstruction()
745 MCB.setOpcode(Hexagon::BUNDLE); in emitInstruction()