Lines Matching refs:Hexagon
118 : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), in HexagonInstrInfo()
128 return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || in isIntRegForSubInst()
129 (Reg >= Hexagon::R16 && Reg <= Hexagon::R23); in isIntRegForSubInst()
133 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) && in isDblRegForSubInst()
134 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi)); in isDblRegForSubInst()
157 if (EndLoopOp == Hexagon::ENDLOOP0) { in findLoopInstr()
158 LOOPi = Hexagon::J2_loop0i; in findLoopInstr()
159 LOOPr = Hexagon::J2_loop0r; in findLoopInstr()
161 LOOPi = Hexagon::J2_loop1i; in findLoopInstr()
162 LOOPr = Hexagon::J2_loop1r; in findLoopInstr()
250 case Hexagon::L2_loadri_io: in isLoadFromStackSlot()
251 case Hexagon::L2_loadrd_io: in isLoadFromStackSlot()
252 case Hexagon::V6_vL32b_ai: in isLoadFromStackSlot()
253 case Hexagon::V6_vL32b_nt_ai: in isLoadFromStackSlot()
254 case Hexagon::V6_vL32Ub_ai: in isLoadFromStackSlot()
255 case Hexagon::LDriw_pred: in isLoadFromStackSlot()
256 case Hexagon::LDriw_ctr: in isLoadFromStackSlot()
257 case Hexagon::PS_vloadrq_ai: in isLoadFromStackSlot()
258 case Hexagon::PS_vloadrw_ai: in isLoadFromStackSlot()
259 case Hexagon::PS_vloadrw_nt_ai: { in isLoadFromStackSlot()
270 case Hexagon::L2_ploadrit_io: in isLoadFromStackSlot()
271 case Hexagon::L2_ploadrif_io: in isLoadFromStackSlot()
272 case Hexagon::L2_ploadrdt_io: in isLoadFromStackSlot()
273 case Hexagon::L2_ploadrdf_io: { in isLoadFromStackSlot()
298 case Hexagon::S2_storerb_io: in isStoreToStackSlot()
299 case Hexagon::S2_storerh_io: in isStoreToStackSlot()
300 case Hexagon::S2_storeri_io: in isStoreToStackSlot()
301 case Hexagon::S2_storerd_io: in isStoreToStackSlot()
302 case Hexagon::V6_vS32b_ai: in isStoreToStackSlot()
303 case Hexagon::V6_vS32Ub_ai: in isStoreToStackSlot()
304 case Hexagon::STriw_pred: in isStoreToStackSlot()
305 case Hexagon::STriw_ctr: in isStoreToStackSlot()
306 case Hexagon::PS_vstorerq_ai: in isStoreToStackSlot()
307 case Hexagon::PS_vstorerw_ai: { in isStoreToStackSlot()
318 case Hexagon::S2_pstorerbt_io: in isStoreToStackSlot()
319 case Hexagon::S2_pstorerbf_io: in isStoreToStackSlot()
320 case Hexagon::S2_pstorerht_io: in isStoreToStackSlot()
321 case Hexagon::S2_pstorerhf_io: in isStoreToStackSlot()
322 case Hexagon::S2_pstorerit_io: in isStoreToStackSlot()
323 case Hexagon::S2_pstorerif_io: in isStoreToStackSlot()
324 case Hexagon::S2_pstorerdt_io: in isStoreToStackSlot()
325 case Hexagon::S2_pstorerdf_io: { in isStoreToStackSlot()
433 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump && in analyzeBranch()
469 if (LastOpcode == Hexagon::J2_jump && !LastInst->getOperand(0).isMBB()) in analyzeBranch()
471 if (SecLastOpcode == Hexagon::J2_jump && in analyzeBranch()
483 if (LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
515 if (SecLastOpcodeHasJMP_c && (LastOpcode == Hexagon::J2_jump)) { in analyzeBranch()
528 (LastOpcode == Hexagon::J2_jump)) { in analyzeBranch()
539 if (SecLastOpcode == Hexagon::J2_jump && LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
548 if (isEndLoopN(SecLastOpcode) && LastOpcode == Hexagon::J2_jump) { in analyzeBranch()
575 if (Count && (I->getOpcode() == Hexagon::J2_jump)) in removeBranch()
590 unsigned BOpc = Hexagon::J2_jump; in insertBranch()
591 unsigned BccOpc = Hexagon::J2_jumpt; in insertBranch()
699 TripCount = Loop->getOpcode() == Hexagon::J2_loop0r in HexagonPipelinerLoopInfo()
718 TII->get(Hexagon::C2_cmpgtui), Done) in createTripCountGreaterCondition()
721 Cond.push_back(MachineOperand::CreateImm(Hexagon::J2_jumpf)); in createTripCountGreaterCondition()
737 if (Loop->getOpcode() == Hexagon::J2_loop0i || in adjustTripCount()
738 Loop->getOpcode() == Hexagon::J2_loop1i) { in adjustTripCount()
750 TII->get(Hexagon::A2_addi), NewLoopCount) in adjustTripCount()
819 if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
820 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg) in copyPhysReg()
824 if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
825 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg) in copyPhysReg()
829 if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
831 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg) in copyPhysReg()
835 if (Hexagon::CtrRegsRegClass.contains(DestReg) && in copyPhysReg()
836 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
837 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg) in copyPhysReg()
841 if (Hexagon::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
842 Hexagon::CtrRegsRegClass.contains(SrcReg)) { in copyPhysReg()
843 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg) in copyPhysReg()
847 if (Hexagon::ModRegsRegClass.contains(DestReg) && in copyPhysReg()
848 Hexagon::IntRegsRegClass.contains(SrcReg)) { in copyPhysReg()
849 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg) in copyPhysReg()
853 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
854 Hexagon::IntRegsRegClass.contains(DestReg)) { in copyPhysReg()
855 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg) in copyPhysReg()
859 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in copyPhysReg()
860 Hexagon::PredRegsRegClass.contains(DestReg)) { in copyPhysReg()
861 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg) in copyPhysReg()
865 if (Hexagon::PredRegsRegClass.contains(SrcReg) && in copyPhysReg()
866 Hexagon::IntRegsRegClass.contains(DestReg)) { in copyPhysReg()
867 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg) in copyPhysReg()
871 if (Hexagon::HvxVRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
872 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg). in copyPhysReg()
876 if (Hexagon::HvxWRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
879 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in copyPhysReg()
880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg()
883 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg) in copyPhysReg()
888 if (Hexagon::HvxQRRegClass.contains(SrcReg, DestReg)) { in copyPhysReg()
889 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg) in copyPhysReg()
894 if (Hexagon::HvxQRRegClass.contains(SrcReg) && in copyPhysReg()
895 Hexagon::HvxVRRegClass.contains(DestReg)) { in copyPhysReg()
899 if (Hexagon::HvxQRRegClass.contains(DestReg) && in copyPhysReg()
900 Hexagon::HvxVRRegClass.contains(SrcReg)) { in copyPhysReg()
925 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
926 BuildMI(MBB, I, DL, get(Hexagon::S2_storeri_io)) in storeRegToStackSlot()
929 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
930 BuildMI(MBB, I, DL, get(Hexagon::S2_storerd_io)) in storeRegToStackSlot()
933 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
934 BuildMI(MBB, I, DL, get(Hexagon::STriw_pred)) in storeRegToStackSlot()
937 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
938 BuildMI(MBB, I, DL, get(Hexagon::STriw_ctr)) in storeRegToStackSlot()
941 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
942 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerq_ai)) in storeRegToStackSlot()
945 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
946 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerv_ai)) in storeRegToStackSlot()
949 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
950 BuildMI(MBB, I, DL, get(Hexagon::PS_vstorerw_ai)) in storeRegToStackSlot()
970 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
971 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg) in loadRegFromStackSlot()
973 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
974 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg) in loadRegFromStackSlot()
976 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
977 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) in loadRegFromStackSlot()
979 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
980 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg) in loadRegFromStackSlot()
982 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
983 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg) in loadRegFromStackSlot()
985 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
986 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrv_ai), DestReg) in loadRegFromStackSlot()
988 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
989 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrw_ai), DestReg) in loadRegFromStackSlot()
1013 unsigned CSx = (Mx == Hexagon::M0 ? Hexagon::CS0 : Hexagon::CS1); in expandPostRAPseudo()
1014 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx) in expandPostRAPseudo()
1045 case Hexagon::PS_aligna: in expandPostRAPseudo()
1046 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1051 case Hexagon::V6_vassignp: { in expandPostRAPseudo()
1054 Register SrcLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1055 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1060 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg) in expandPostRAPseudo()
1066 case Hexagon::V6_lo: { in expandPostRAPseudo()
1069 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo); in expandPostRAPseudo()
1075 case Hexagon::V6_hi: { in expandPostRAPseudo()
1078 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo()
1084 case Hexagon::PS_vloadrv_ai: { in expandPostRAPseudo()
1089 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1090 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1091 : Hexagon::V6_vL32Ub_ai; in expandPostRAPseudo()
1099 case Hexagon::PS_vloadrw_ai: { in expandPostRAPseudo()
1104 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1105 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1106 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1107 : Hexagon::V6_vL32Ub_ai; in expandPostRAPseudo()
1109 HRI.getSubReg(DstReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1114 HRI.getSubReg(DstReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1121 case Hexagon::PS_vstorerv_ai: { in expandPostRAPseudo()
1127 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1128 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1129 : Hexagon::V6_vS32Ub_ai; in expandPostRAPseudo()
1138 case Hexagon::PS_vstorerw_ai: { in expandPostRAPseudo()
1143 unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1144 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
1145 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1146 : Hexagon::V6_vS32Ub_ai; in expandPostRAPseudo()
1150 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1155 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi)) in expandPostRAPseudo()
1160 case Hexagon::PS_true: { in expandPostRAPseudo()
1162 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg) in expandPostRAPseudo()
1168 case Hexagon::PS_false: { in expandPostRAPseudo()
1170 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg) in expandPostRAPseudo()
1176 case Hexagon::PS_qtrue: { in expandPostRAPseudo()
1177 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1178 .addReg(Hexagon::V0, RegState::Undef) in expandPostRAPseudo()
1179 .addReg(Hexagon::V0, RegState::Undef); in expandPostRAPseudo()
1183 case Hexagon::PS_qfalse: { in expandPostRAPseudo()
1184 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg()) in expandPostRAPseudo()
1185 .addReg(Hexagon::V0, RegState::Undef) in expandPostRAPseudo()
1186 .addReg(Hexagon::V0, RegState::Undef); in expandPostRAPseudo()
1190 case Hexagon::PS_vdd0: { in expandPostRAPseudo()
1192 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1198 case Hexagon::PS_vmulw: { in expandPostRAPseudo()
1203 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1204 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1205 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1206 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1207 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi), in expandPostRAPseudo()
1208 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1211 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi), in expandPostRAPseudo()
1212 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1222 case Hexagon::PS_vmulw_acc: { in expandPostRAPseudo()
1228 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1229 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1230 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1231 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1232 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi); in expandPostRAPseudo()
1233 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo); in expandPostRAPseudo()
1234 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci), in expandPostRAPseudo()
1235 HRI.getSubReg(DstReg, Hexagon::isub_hi)) in expandPostRAPseudo()
1239 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci), in expandPostRAPseudo()
1240 HRI.getSubReg(DstReg, Hexagon::isub_lo)) in expandPostRAPseudo()
1253 case Hexagon::PS_pselect: { in expandPostRAPseudo()
1267 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd) in expandPostRAPseudo()
1271 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd) in expandPostRAPseudo()
1277 case Hexagon::PS_vselect: { in expandPostRAPseudo()
1291 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov)) in expandPostRAPseudo()
1300 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov)) in expandPostRAPseudo()
1310 case Hexagon::PS_wselect: { in expandPostRAPseudo()
1324 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1325 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1326 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine)) in expandPostRAPseudo()
1336 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo); in expandPostRAPseudo()
1337 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo()
1338 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine)) in expandPostRAPseudo()
1350 case Hexagon::PS_crash: { in expandPostRAPseudo()
1376 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13) in expandPostRAPseudo()
1383 case Hexagon::PS_tailcall_i: in expandPostRAPseudo()
1384 MI.setDesc(get(Hexagon::J2_jump)); in expandPostRAPseudo()
1386 case Hexagon::PS_tailcall_r: in expandPostRAPseudo()
1387 case Hexagon::PS_jmpret: in expandPostRAPseudo()
1388 MI.setDesc(get(Hexagon::J2_jumpr)); in expandPostRAPseudo()
1390 case Hexagon::PS_jmprett: in expandPostRAPseudo()
1391 MI.setDesc(get(Hexagon::J2_jumprt)); in expandPostRAPseudo()
1393 case Hexagon::PS_jmpretf: in expandPostRAPseudo()
1394 MI.setDesc(get(Hexagon::J2_jumprf)); in expandPostRAPseudo()
1396 case Hexagon::PS_jmprettnewpt: in expandPostRAPseudo()
1397 MI.setDesc(get(Hexagon::J2_jumprtnewpt)); in expandPostRAPseudo()
1399 case Hexagon::PS_jmpretfnewpt: in expandPostRAPseudo()
1400 MI.setDesc(get(Hexagon::J2_jumprfnewpt)); in expandPostRAPseudo()
1402 case Hexagon::PS_jmprettnew: in expandPostRAPseudo()
1403 MI.setDesc(get(Hexagon::J2_jumprtnew)); in expandPostRAPseudo()
1405 case Hexagon::PS_jmpretfnew: in expandPostRAPseudo()
1406 MI.setDesc(get(Hexagon::J2_jumprfnew)); in expandPostRAPseudo()
1409 case Hexagon::PS_loadrub_pci: in expandPostRAPseudo()
1410 return RealCirc(Hexagon::L2_loadrub_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1411 case Hexagon::PS_loadrb_pci: in expandPostRAPseudo()
1412 return RealCirc(Hexagon::L2_loadrb_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1413 case Hexagon::PS_loadruh_pci: in expandPostRAPseudo()
1414 return RealCirc(Hexagon::L2_loadruh_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1415 case Hexagon::PS_loadrh_pci: in expandPostRAPseudo()
1416 return RealCirc(Hexagon::L2_loadrh_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1417 case Hexagon::PS_loadri_pci: in expandPostRAPseudo()
1418 return RealCirc(Hexagon::L2_loadri_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1419 case Hexagon::PS_loadrd_pci: in expandPostRAPseudo()
1420 return RealCirc(Hexagon::L2_loadrd_pci, /*HasImm*/true, /*MxOp*/4); in expandPostRAPseudo()
1421 case Hexagon::PS_loadrub_pcr: in expandPostRAPseudo()
1422 return RealCirc(Hexagon::L2_loadrub_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1423 case Hexagon::PS_loadrb_pcr: in expandPostRAPseudo()
1424 return RealCirc(Hexagon::L2_loadrb_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1425 case Hexagon::PS_loadruh_pcr: in expandPostRAPseudo()
1426 return RealCirc(Hexagon::L2_loadruh_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1427 case Hexagon::PS_loadrh_pcr: in expandPostRAPseudo()
1428 return RealCirc(Hexagon::L2_loadrh_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1429 case Hexagon::PS_loadri_pcr: in expandPostRAPseudo()
1430 return RealCirc(Hexagon::L2_loadri_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1431 case Hexagon::PS_loadrd_pcr: in expandPostRAPseudo()
1432 return RealCirc(Hexagon::L2_loadrd_pcr, /*HasImm*/false, /*MxOp*/3); in expandPostRAPseudo()
1433 case Hexagon::PS_storerb_pci: in expandPostRAPseudo()
1434 return RealCirc(Hexagon::S2_storerb_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1435 case Hexagon::PS_storerh_pci: in expandPostRAPseudo()
1436 return RealCirc(Hexagon::S2_storerh_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1437 case Hexagon::PS_storerf_pci: in expandPostRAPseudo()
1438 return RealCirc(Hexagon::S2_storerf_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1439 case Hexagon::PS_storeri_pci: in expandPostRAPseudo()
1440 return RealCirc(Hexagon::S2_storeri_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1441 case Hexagon::PS_storerd_pci: in expandPostRAPseudo()
1442 return RealCirc(Hexagon::S2_storerd_pci, /*HasImm*/true, /*MxOp*/3); in expandPostRAPseudo()
1443 case Hexagon::PS_storerb_pcr: in expandPostRAPseudo()
1444 return RealCirc(Hexagon::S2_storerb_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1445 case Hexagon::PS_storerh_pcr: in expandPostRAPseudo()
1446 return RealCirc(Hexagon::S2_storerh_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1447 case Hexagon::PS_storerf_pcr: in expandPostRAPseudo()
1448 return RealCirc(Hexagon::S2_storerf_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1449 case Hexagon::PS_storeri_pcr: in expandPostRAPseudo()
1450 return RealCirc(Hexagon::S2_storeri_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1451 case Hexagon::PS_storerd_pcr: in expandPostRAPseudo()
1452 return RealCirc(Hexagon::S2_storerd_pcr, /*HasImm*/false, /*MxOp*/2); in expandPostRAPseudo()
1466 case Hexagon::V6_vgathermh_pseudo: in expandVGatherPseudo()
1467 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermh)) in expandVGatherPseudo()
1471 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1474 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1478 case Hexagon::V6_vgathermw_pseudo: in expandVGatherPseudo()
1479 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermw)) in expandVGatherPseudo()
1483 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1486 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1490 case Hexagon::V6_vgathermhw_pseudo: in expandVGatherPseudo()
1491 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhw)) in expandVGatherPseudo()
1495 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1498 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1502 case Hexagon::V6_vgathermhq_pseudo: in expandVGatherPseudo()
1503 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhq)) in expandVGatherPseudo()
1508 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1511 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1515 case Hexagon::V6_vgathermwq_pseudo: in expandVGatherPseudo()
1516 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermwq)) in expandVGatherPseudo()
1521 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1524 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1528 case Hexagon::V6_vgathermhwq_pseudo: in expandVGatherPseudo()
1529 First = BuildMI(MBB, MI, DL, get(Hexagon::V6_vgathermhwq)) in expandVGatherPseudo()
1534 BuildMI(MBB, MI, DL, get(Hexagon::V6_vS32b_new_ai)) in expandVGatherPseudo()
1537 .addReg(Hexagon::VTMP); in expandVGatherPseudo()
1565 BuildMI(MBB, MI, DL, get(Hexagon::A2_nop)); in insertNoop()
1653 if (RC == &Hexagon::PredRegsRegClass) { in ClobbersPredicate()
1659 for (unsigned PR : Hexagon::PredRegsRegClass) { in ClobbersPredicate()
1682 case Hexagon::V6_vL32b_ai: in isPredicable()
1683 case Hexagon::V6_vL32b_pi: in isPredicable()
1684 case Hexagon::V6_vL32b_ppu: in isPredicable()
1685 case Hexagon::V6_vL32b_cur_ai: in isPredicable()
1686 case Hexagon::V6_vL32b_cur_pi: in isPredicable()
1687 case Hexagon::V6_vL32b_cur_ppu: in isPredicable()
1688 case Hexagon::V6_vL32b_nt_ai: in isPredicable()
1689 case Hexagon::V6_vL32b_nt_pi: in isPredicable()
1690 case Hexagon::V6_vL32b_nt_ppu: in isPredicable()
1691 case Hexagon::V6_vL32b_tmp_ai: in isPredicable()
1692 case Hexagon::V6_vL32b_tmp_pi: in isPredicable()
1693 case Hexagon::V6_vL32b_tmp_ppu: in isPredicable()
1694 case Hexagon::V6_vL32b_nt_cur_ai: in isPredicable()
1695 case Hexagon::V6_vL32b_nt_cur_pi: in isPredicable()
1696 case Hexagon::V6_vL32b_nt_cur_ppu: in isPredicable()
1697 case Hexagon::V6_vL32b_nt_tmp_ai: in isPredicable()
1698 case Hexagon::V6_vL32b_nt_tmp_pi: in isPredicable()
1699 case Hexagon::V6_vL32b_nt_tmp_ppu: in isPredicable()
1800 case Hexagon::C2_cmpeq: in analyzeCompare()
1801 case Hexagon::C2_cmpeqp: in analyzeCompare()
1802 case Hexagon::C2_cmpgt: in analyzeCompare()
1803 case Hexagon::C2_cmpgtp: in analyzeCompare()
1804 case Hexagon::C2_cmpgtu: in analyzeCompare()
1805 case Hexagon::C2_cmpgtup: in analyzeCompare()
1806 case Hexagon::C4_cmpneq: in analyzeCompare()
1807 case Hexagon::C4_cmplte: in analyzeCompare()
1808 case Hexagon::C4_cmplteu: in analyzeCompare()
1809 case Hexagon::C2_cmpeqi: in analyzeCompare()
1810 case Hexagon::C2_cmpgti: in analyzeCompare()
1811 case Hexagon::C2_cmpgtui: in analyzeCompare()
1812 case Hexagon::C4_cmpneqi: in analyzeCompare()
1813 case Hexagon::C4_cmplteui: in analyzeCompare()
1814 case Hexagon::C4_cmpltei: in analyzeCompare()
1818 case Hexagon::A4_cmpbeq: in analyzeCompare()
1819 case Hexagon::A4_cmpbgt: in analyzeCompare()
1820 case Hexagon::A4_cmpbgtu: in analyzeCompare()
1821 case Hexagon::A4_cmpbeqi: in analyzeCompare()
1822 case Hexagon::A4_cmpbgti: in analyzeCompare()
1823 case Hexagon::A4_cmpbgtui: in analyzeCompare()
1827 case Hexagon::A4_cmpheq: in analyzeCompare()
1828 case Hexagon::A4_cmphgt: in analyzeCompare()
1829 case Hexagon::A4_cmphgtu: in analyzeCompare()
1830 case Hexagon::A4_cmpheqi: in analyzeCompare()
1831 case Hexagon::A4_cmphgti: in analyzeCompare()
1832 case Hexagon::A4_cmphgtui: in analyzeCompare()
1840 case Hexagon::C2_cmpeq: in analyzeCompare()
1841 case Hexagon::C2_cmpeqp: in analyzeCompare()
1842 case Hexagon::C2_cmpgt: in analyzeCompare()
1843 case Hexagon::C2_cmpgtp: in analyzeCompare()
1844 case Hexagon::C2_cmpgtu: in analyzeCompare()
1845 case Hexagon::C2_cmpgtup: in analyzeCompare()
1846 case Hexagon::A4_cmpbeq: in analyzeCompare()
1847 case Hexagon::A4_cmpbgt: in analyzeCompare()
1848 case Hexagon::A4_cmpbgtu: in analyzeCompare()
1849 case Hexagon::A4_cmpheq: in analyzeCompare()
1850 case Hexagon::A4_cmphgt: in analyzeCompare()
1851 case Hexagon::A4_cmphgtu: in analyzeCompare()
1852 case Hexagon::C4_cmpneq: in analyzeCompare()
1853 case Hexagon::C4_cmplte: in analyzeCompare()
1854 case Hexagon::C4_cmplteu: in analyzeCompare()
1858 case Hexagon::C2_cmpeqi: in analyzeCompare()
1859 case Hexagon::C2_cmpgtui: in analyzeCompare()
1860 case Hexagon::C2_cmpgti: in analyzeCompare()
1861 case Hexagon::C4_cmpneqi: in analyzeCompare()
1862 case Hexagon::C4_cmplteui: in analyzeCompare()
1863 case Hexagon::C4_cmpltei: in analyzeCompare()
1864 case Hexagon::A4_cmpbeqi: in analyzeCompare()
1865 case Hexagon::A4_cmpbgti: in analyzeCompare()
1866 case Hexagon::A4_cmpbgtui: in analyzeCompare()
1867 case Hexagon::A4_cmpheqi: in analyzeCompare()
1868 case Hexagon::A4_cmphgti: in analyzeCompare()
1869 case Hexagon::A4_cmphgtui: { in analyzeCompare()
1967 } else if (MI.getOpcode() == Hexagon::A2_addi) { in getIncrementValue()
2017 TRC = &Hexagon::PredRegsRegClass; in createVR()
2019 TRC = &Hexagon::IntRegsRegClass; in createVR()
2021 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
2046 MI.getDesc().getOpcode() != Hexagon::S2_allocframe && in isComplex()
2047 MI.getDesc().getOpcode() != Hexagon::L2_deallocframe && in isComplex()
2103 case Hexagon::L4_return: in isDeallocRet()
2104 case Hexagon::L4_return_t: in isDeallocRet()
2105 case Hexagon::L4_return_f: in isDeallocRet()
2106 case Hexagon::L4_return_tnew_pnt: in isDeallocRet()
2107 case Hexagon::L4_return_fnew_pnt: in isDeallocRet()
2108 case Hexagon::L4_return_tnew_pt: in isDeallocRet()
2109 case Hexagon::L4_return_fnew_pt: in isDeallocRet()
2153 case Hexagon::V6_vL32b_cur_pi: in isDotCurInst()
2154 case Hexagon::V6_vL32b_cur_ai: in isDotCurInst()
2187 return (Opcode == Hexagon::ENDLOOP0 || in isEndLoopN()
2188 Opcode == Hexagon::ENDLOOP1); in isEndLoopN()
2215 case Hexagon::PS_fi: in isExtendable()
2216 case Hexagon::PS_fia: in isExtendable()
2258 case Hexagon::J2_callr: in isIndirectCall()
2259 case Hexagon::J2_callrf: in isIndirectCall()
2260 case Hexagon::J2_callrt: in isIndirectCall()
2261 case Hexagon::PS_call_nr: in isIndirectCall()
2269 case Hexagon::L4_return: in isIndirectL4Return()
2270 case Hexagon::L4_return_t: in isIndirectL4Return()
2271 case Hexagon::L4_return_f: in isIndirectL4Return()
2272 case Hexagon::L4_return_fnew_pnt: in isIndirectL4Return()
2273 case Hexagon::L4_return_fnew_pt: in isIndirectL4Return()
2274 case Hexagon::L4_return_tnew_pnt: in isIndirectL4Return()
2275 case Hexagon::L4_return_tnew_pt: in isIndirectL4Return()
2283 case Hexagon::J2_jumpr: in isJumpR()
2284 case Hexagon::J2_jumprt: in isJumpR()
2285 case Hexagon::J2_jumprf: in isJumpR()
2286 case Hexagon::J2_jumprtnewpt: in isJumpR()
2287 case Hexagon::J2_jumprfnewpt: in isJumpR()
2288 case Hexagon::J2_jumprtnew: in isJumpR()
2289 case Hexagon::J2_jumprfnew: in isJumpR()
2310 case Hexagon::J2_jump: // bits<24> dst; // r22:2 in isJumpWithinBranchRange()
2311 case Hexagon::J2_call: in isJumpWithinBranchRange()
2312 case Hexagon::PS_call_nr: in isJumpWithinBranchRange()
2314 case Hexagon::J2_jumpt: //bits<17> dst; // r15:2 in isJumpWithinBranchRange()
2315 case Hexagon::J2_jumpf: in isJumpWithinBranchRange()
2316 case Hexagon::J2_jumptnew: in isJumpWithinBranchRange()
2317 case Hexagon::J2_jumptnewpt: in isJumpWithinBranchRange()
2318 case Hexagon::J2_jumpfnew: in isJumpWithinBranchRange()
2319 case Hexagon::J2_jumpfnewpt: in isJumpWithinBranchRange()
2320 case Hexagon::J2_callt: in isJumpWithinBranchRange()
2321 case Hexagon::J2_callf: in isJumpWithinBranchRange()
2323 case Hexagon::J2_loop0i: in isJumpWithinBranchRange()
2324 case Hexagon::J2_loop0iext: in isJumpWithinBranchRange()
2325 case Hexagon::J2_loop0r: in isJumpWithinBranchRange()
2326 case Hexagon::J2_loop0rext: in isJumpWithinBranchRange()
2327 case Hexagon::J2_loop1i: in isJumpWithinBranchRange()
2328 case Hexagon::J2_loop1iext: in isJumpWithinBranchRange()
2329 case Hexagon::J2_loop1r: in isJumpWithinBranchRange()
2330 case Hexagon::J2_loop1rext: in isJumpWithinBranchRange()
2333 case Hexagon::J4_cmpeqi_tp0_jump_nt: in isJumpWithinBranchRange()
2334 case Hexagon::J4_cmpeqi_tp1_jump_nt: in isJumpWithinBranchRange()
2335 case Hexagon::J4_cmpeqn1_tp0_jump_nt: in isJumpWithinBranchRange()
2336 case Hexagon::J4_cmpeqn1_tp1_jump_nt: in isJumpWithinBranchRange()
2386 return Opcode == Hexagon::J2_loop0i || in isLoopN()
2387 Opcode == Hexagon::J2_loop0r || in isLoopN()
2388 Opcode == Hexagon::J2_loop0iext || in isLoopN()
2389 Opcode == Hexagon::J2_loop0rext || in isLoopN()
2390 Opcode == Hexagon::J2_loop1i || in isLoopN()
2391 Opcode == Hexagon::J2_loop1r || in isLoopN()
2392 Opcode == Hexagon::J2_loop1iext || in isLoopN()
2393 Opcode == Hexagon::J2_loop1rext; in isLoopN()
2399 case Hexagon::L4_iadd_memopw_io: in isMemOp()
2400 case Hexagon::L4_isub_memopw_io: in isMemOp()
2401 case Hexagon::L4_add_memopw_io: in isMemOp()
2402 case Hexagon::L4_sub_memopw_io: in isMemOp()
2403 case Hexagon::L4_and_memopw_io: in isMemOp()
2404 case Hexagon::L4_or_memopw_io: in isMemOp()
2405 case Hexagon::L4_iadd_memoph_io: in isMemOp()
2406 case Hexagon::L4_isub_memoph_io: in isMemOp()
2407 case Hexagon::L4_add_memoph_io: in isMemOp()
2408 case Hexagon::L4_sub_memoph_io: in isMemOp()
2409 case Hexagon::L4_and_memoph_io: in isMemOp()
2410 case Hexagon::L4_or_memoph_io: in isMemOp()
2411 case Hexagon::L4_iadd_memopb_io: in isMemOp()
2412 case Hexagon::L4_isub_memopb_io: in isMemOp()
2413 case Hexagon::L4_add_memopb_io: in isMemOp()
2414 case Hexagon::L4_sub_memopb_io: in isMemOp()
2415 case Hexagon::L4_and_memopb_io: in isMemOp()
2416 case Hexagon::L4_or_memopb_io: in isMemOp()
2417 case Hexagon::L4_ior_memopb_io: in isMemOp()
2418 case Hexagon::L4_ior_memoph_io: in isMemOp()
2419 case Hexagon::L4_ior_memopw_io: in isMemOp()
2420 case Hexagon::L4_iand_memopb_io: in isMemOp()
2421 case Hexagon::L4_iand_memoph_io: in isMemOp()
2422 case Hexagon::L4_iand_memopw_io: in isMemOp()
2512 return MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4 || in isSaveCalleeSavedRegsCall()
2513 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT || in isSaveCalleeSavedRegsCall()
2514 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_PIC || in isSaveCalleeSavedRegsCall()
2515 MI.getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4_EXT_PIC; in isSaveCalleeSavedRegsCall()
2521 case Hexagon::L2_loadrb_io: in isSignExtendingLoad()
2522 case Hexagon::L4_loadrb_ur: in isSignExtendingLoad()
2523 case Hexagon::L4_loadrb_ap: in isSignExtendingLoad()
2524 case Hexagon::L2_loadrb_pr: in isSignExtendingLoad()
2525 case Hexagon::L2_loadrb_pbr: in isSignExtendingLoad()
2526 case Hexagon::L2_loadrb_pi: in isSignExtendingLoad()
2527 case Hexagon::L2_loadrb_pci: in isSignExtendingLoad()
2528 case Hexagon::L2_loadrb_pcr: in isSignExtendingLoad()
2529 case Hexagon::L2_loadbsw2_io: in isSignExtendingLoad()
2530 case Hexagon::L4_loadbsw2_ur: in isSignExtendingLoad()
2531 case Hexagon::L4_loadbsw2_ap: in isSignExtendingLoad()
2532 case Hexagon::L2_loadbsw2_pr: in isSignExtendingLoad()
2533 case Hexagon::L2_loadbsw2_pbr: in isSignExtendingLoad()
2534 case Hexagon::L2_loadbsw2_pi: in isSignExtendingLoad()
2535 case Hexagon::L2_loadbsw2_pci: in isSignExtendingLoad()
2536 case Hexagon::L2_loadbsw2_pcr: in isSignExtendingLoad()
2537 case Hexagon::L2_loadbsw4_io: in isSignExtendingLoad()
2538 case Hexagon::L4_loadbsw4_ur: in isSignExtendingLoad()
2539 case Hexagon::L4_loadbsw4_ap: in isSignExtendingLoad()
2540 case Hexagon::L2_loadbsw4_pr: in isSignExtendingLoad()
2541 case Hexagon::L2_loadbsw4_pbr: in isSignExtendingLoad()
2542 case Hexagon::L2_loadbsw4_pi: in isSignExtendingLoad()
2543 case Hexagon::L2_loadbsw4_pci: in isSignExtendingLoad()
2544 case Hexagon::L2_loadbsw4_pcr: in isSignExtendingLoad()
2545 case Hexagon::L4_loadrb_rr: in isSignExtendingLoad()
2546 case Hexagon::L2_ploadrbt_io: in isSignExtendingLoad()
2547 case Hexagon::L2_ploadrbt_pi: in isSignExtendingLoad()
2548 case Hexagon::L2_ploadrbf_io: in isSignExtendingLoad()
2549 case Hexagon::L2_ploadrbf_pi: in isSignExtendingLoad()
2550 case Hexagon::L2_ploadrbtnew_io: in isSignExtendingLoad()
2551 case Hexagon::L2_ploadrbfnew_io: in isSignExtendingLoad()
2552 case Hexagon::L4_ploadrbt_rr: in isSignExtendingLoad()
2553 case Hexagon::L4_ploadrbf_rr: in isSignExtendingLoad()
2554 case Hexagon::L4_ploadrbtnew_rr: in isSignExtendingLoad()
2555 case Hexagon::L4_ploadrbfnew_rr: in isSignExtendingLoad()
2556 case Hexagon::L2_ploadrbtnew_pi: in isSignExtendingLoad()
2557 case Hexagon::L2_ploadrbfnew_pi: in isSignExtendingLoad()
2558 case Hexagon::L4_ploadrbt_abs: in isSignExtendingLoad()
2559 case Hexagon::L4_ploadrbf_abs: in isSignExtendingLoad()
2560 case Hexagon::L4_ploadrbtnew_abs: in isSignExtendingLoad()
2561 case Hexagon::L4_ploadrbfnew_abs: in isSignExtendingLoad()
2562 case Hexagon::L2_loadrbgp: in isSignExtendingLoad()
2564 case Hexagon::L2_loadrh_io: in isSignExtendingLoad()
2565 case Hexagon::L4_loadrh_ur: in isSignExtendingLoad()
2566 case Hexagon::L4_loadrh_ap: in isSignExtendingLoad()
2567 case Hexagon::L2_loadrh_pr: in isSignExtendingLoad()
2568 case Hexagon::L2_loadrh_pbr: in isSignExtendingLoad()
2569 case Hexagon::L2_loadrh_pi: in isSignExtendingLoad()
2570 case Hexagon::L2_loadrh_pci: in isSignExtendingLoad()
2571 case Hexagon::L2_loadrh_pcr: in isSignExtendingLoad()
2572 case Hexagon::L4_loadrh_rr: in isSignExtendingLoad()
2573 case Hexagon::L2_ploadrht_io: in isSignExtendingLoad()
2574 case Hexagon::L2_ploadrht_pi: in isSignExtendingLoad()
2575 case Hexagon::L2_ploadrhf_io: in isSignExtendingLoad()
2576 case Hexagon::L2_ploadrhf_pi: in isSignExtendingLoad()
2577 case Hexagon::L2_ploadrhtnew_io: in isSignExtendingLoad()
2578 case Hexagon::L2_ploadrhfnew_io: in isSignExtendingLoad()
2579 case Hexagon::L4_ploadrht_rr: in isSignExtendingLoad()
2580 case Hexagon::L4_ploadrhf_rr: in isSignExtendingLoad()
2581 case Hexagon::L4_ploadrhtnew_rr: in isSignExtendingLoad()
2582 case Hexagon::L4_ploadrhfnew_rr: in isSignExtendingLoad()
2583 case Hexagon::L2_ploadrhtnew_pi: in isSignExtendingLoad()
2584 case Hexagon::L2_ploadrhfnew_pi: in isSignExtendingLoad()
2585 case Hexagon::L4_ploadrht_abs: in isSignExtendingLoad()
2586 case Hexagon::L4_ploadrhf_abs: in isSignExtendingLoad()
2587 case Hexagon::L4_ploadrhtnew_abs: in isSignExtendingLoad()
2588 case Hexagon::L4_ploadrhfnew_abs: in isSignExtendingLoad()
2589 case Hexagon::L2_loadrhgp: in isSignExtendingLoad()
2603 case Hexagon::STriw_pred: in isSpillPredRegOp()
2604 case Hexagon::LDriw_pred: in isSpillPredRegOp()
2654 if (MI2.getOpcode() == Hexagon::V6_vS32b_pi) in isToBeScheduledASAP()
2715 case Hexagon::PS_vstorerq_ai: in isValidOffset()
2716 case Hexagon::PS_vstorerv_ai: in isValidOffset()
2717 case Hexagon::PS_vstorerw_ai: in isValidOffset()
2718 case Hexagon::PS_vstorerw_nt_ai: in isValidOffset()
2719 case Hexagon::PS_vloadrq_ai: in isValidOffset()
2720 case Hexagon::PS_vloadrv_ai: in isValidOffset()
2721 case Hexagon::PS_vloadrw_ai: in isValidOffset()
2722 case Hexagon::PS_vloadrw_nt_ai: in isValidOffset()
2723 case Hexagon::V6_vL32b_ai: in isValidOffset()
2724 case Hexagon::V6_vS32b_ai: in isValidOffset()
2725 case Hexagon::V6_vS32b_qpred_ai: in isValidOffset()
2726 case Hexagon::V6_vS32b_nqpred_ai: in isValidOffset()
2727 case Hexagon::V6_vL32b_nt_ai: in isValidOffset()
2728 case Hexagon::V6_vS32b_nt_ai: in isValidOffset()
2729 case Hexagon::V6_vL32Ub_ai: in isValidOffset()
2730 case Hexagon::V6_vS32Ub_ai: { in isValidOffset()
2731 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); in isValidOffset()
2738 case Hexagon::J2_loop0i: in isValidOffset()
2739 case Hexagon::J2_loop1i: in isValidOffset()
2742 case Hexagon::S4_storeirb_io: in isValidOffset()
2743 case Hexagon::S4_storeirbt_io: in isValidOffset()
2744 case Hexagon::S4_storeirbf_io: in isValidOffset()
2747 case Hexagon::S4_storeirh_io: in isValidOffset()
2748 case Hexagon::S4_storeirht_io: in isValidOffset()
2749 case Hexagon::S4_storeirhf_io: in isValidOffset()
2752 case Hexagon::S4_storeiri_io: in isValidOffset()
2753 case Hexagon::S4_storeirit_io: in isValidOffset()
2754 case Hexagon::S4_storeirif_io: in isValidOffset()
2762 case Hexagon::L2_loadri_io: in isValidOffset()
2763 case Hexagon::S2_storeri_io: in isValidOffset()
2767 case Hexagon::L2_loadrd_io: in isValidOffset()
2768 case Hexagon::S2_storerd_io: in isValidOffset()
2772 case Hexagon::L2_loadrh_io: in isValidOffset()
2773 case Hexagon::L2_loadruh_io: in isValidOffset()
2774 case Hexagon::S2_storerh_io: in isValidOffset()
2775 case Hexagon::S2_storerf_io: in isValidOffset()
2779 case Hexagon::L2_loadrb_io: in isValidOffset()
2780 case Hexagon::L2_loadrub_io: in isValidOffset()
2781 case Hexagon::S2_storerb_io: in isValidOffset()
2785 case Hexagon::A2_addi: in isValidOffset()
2789 case Hexagon::L4_iadd_memopw_io: in isValidOffset()
2790 case Hexagon::L4_isub_memopw_io: in isValidOffset()
2791 case Hexagon::L4_add_memopw_io: in isValidOffset()
2792 case Hexagon::L4_sub_memopw_io: in isValidOffset()
2793 case Hexagon::L4_and_memopw_io: in isValidOffset()
2794 case Hexagon::L4_or_memopw_io: in isValidOffset()
2797 case Hexagon::L4_iadd_memoph_io: in isValidOffset()
2798 case Hexagon::L4_isub_memoph_io: in isValidOffset()
2799 case Hexagon::L4_add_memoph_io: in isValidOffset()
2800 case Hexagon::L4_sub_memoph_io: in isValidOffset()
2801 case Hexagon::L4_and_memoph_io: in isValidOffset()
2802 case Hexagon::L4_or_memoph_io: in isValidOffset()
2805 case Hexagon::L4_iadd_memopb_io: in isValidOffset()
2806 case Hexagon::L4_isub_memopb_io: in isValidOffset()
2807 case Hexagon::L4_add_memopb_io: in isValidOffset()
2808 case Hexagon::L4_sub_memopb_io: in isValidOffset()
2809 case Hexagon::L4_and_memopb_io: in isValidOffset()
2810 case Hexagon::L4_or_memopb_io: in isValidOffset()
2815 case Hexagon::STriw_pred: in isValidOffset()
2816 case Hexagon::LDriw_pred: in isValidOffset()
2817 case Hexagon::STriw_ctr: in isValidOffset()
2818 case Hexagon::LDriw_ctr: in isValidOffset()
2821 case Hexagon::PS_fi: in isValidOffset()
2822 case Hexagon::PS_fia: in isValidOffset()
2823 case Hexagon::INLINEASM: in isValidOffset()
2826 case Hexagon::L2_ploadrbt_io: in isValidOffset()
2827 case Hexagon::L2_ploadrbf_io: in isValidOffset()
2828 case Hexagon::L2_ploadrubt_io: in isValidOffset()
2829 case Hexagon::L2_ploadrubf_io: in isValidOffset()
2830 case Hexagon::S2_pstorerbt_io: in isValidOffset()
2831 case Hexagon::S2_pstorerbf_io: in isValidOffset()
2834 case Hexagon::L2_ploadrht_io: in isValidOffset()
2835 case Hexagon::L2_ploadrhf_io: in isValidOffset()
2836 case Hexagon::L2_ploadruht_io: in isValidOffset()
2837 case Hexagon::L2_ploadruhf_io: in isValidOffset()
2838 case Hexagon::S2_pstorerht_io: in isValidOffset()
2839 case Hexagon::S2_pstorerhf_io: in isValidOffset()
2842 case Hexagon::L2_ploadrit_io: in isValidOffset()
2843 case Hexagon::L2_ploadrif_io: in isValidOffset()
2844 case Hexagon::S2_pstorerit_io: in isValidOffset()
2845 case Hexagon::S2_pstorerif_io: in isValidOffset()
2848 case Hexagon::L2_ploadrdt_io: in isValidOffset()
2849 case Hexagon::L2_ploadrdf_io: in isValidOffset()
2850 case Hexagon::S2_pstorerdt_io: in isValidOffset()
2851 case Hexagon::S2_pstorerdf_io: in isValidOffset()
2888 case Hexagon::L2_loadrub_io: in isZeroExtendingLoad()
2889 case Hexagon::L4_loadrub_ur: in isZeroExtendingLoad()
2890 case Hexagon::L4_loadrub_ap: in isZeroExtendingLoad()
2891 case Hexagon::L2_loadrub_pr: in isZeroExtendingLoad()
2892 case Hexagon::L2_loadrub_pbr: in isZeroExtendingLoad()
2893 case Hexagon::L2_loadrub_pi: in isZeroExtendingLoad()
2894 case Hexagon::L2_loadrub_pci: in isZeroExtendingLoad()
2895 case Hexagon::L2_loadrub_pcr: in isZeroExtendingLoad()
2896 case Hexagon::L2_loadbzw2_io: in isZeroExtendingLoad()
2897 case Hexagon::L4_loadbzw2_ur: in isZeroExtendingLoad()
2898 case Hexagon::L4_loadbzw2_ap: in isZeroExtendingLoad()
2899 case Hexagon::L2_loadbzw2_pr: in isZeroExtendingLoad()
2900 case Hexagon::L2_loadbzw2_pbr: in isZeroExtendingLoad()
2901 case Hexagon::L2_loadbzw2_pi: in isZeroExtendingLoad()
2902 case Hexagon::L2_loadbzw2_pci: in isZeroExtendingLoad()
2903 case Hexagon::L2_loadbzw2_pcr: in isZeroExtendingLoad()
2904 case Hexagon::L2_loadbzw4_io: in isZeroExtendingLoad()
2905 case Hexagon::L4_loadbzw4_ur: in isZeroExtendingLoad()
2906 case Hexagon::L4_loadbzw4_ap: in isZeroExtendingLoad()
2907 case Hexagon::L2_loadbzw4_pr: in isZeroExtendingLoad()
2908 case Hexagon::L2_loadbzw4_pbr: in isZeroExtendingLoad()
2909 case Hexagon::L2_loadbzw4_pi: in isZeroExtendingLoad()
2910 case Hexagon::L2_loadbzw4_pci: in isZeroExtendingLoad()
2911 case Hexagon::L2_loadbzw4_pcr: in isZeroExtendingLoad()
2912 case Hexagon::L4_loadrub_rr: in isZeroExtendingLoad()
2913 case Hexagon::L2_ploadrubt_io: in isZeroExtendingLoad()
2914 case Hexagon::L2_ploadrubt_pi: in isZeroExtendingLoad()
2915 case Hexagon::L2_ploadrubf_io: in isZeroExtendingLoad()
2916 case Hexagon::L2_ploadrubf_pi: in isZeroExtendingLoad()
2917 case Hexagon::L2_ploadrubtnew_io: in isZeroExtendingLoad()
2918 case Hexagon::L2_ploadrubfnew_io: in isZeroExtendingLoad()
2919 case Hexagon::L4_ploadrubt_rr: in isZeroExtendingLoad()
2920 case Hexagon::L4_ploadrubf_rr: in isZeroExtendingLoad()
2921 case Hexagon::L4_ploadrubtnew_rr: in isZeroExtendingLoad()
2922 case Hexagon::L4_ploadrubfnew_rr: in isZeroExtendingLoad()
2923 case Hexagon::L2_ploadrubtnew_pi: in isZeroExtendingLoad()
2924 case Hexagon::L2_ploadrubfnew_pi: in isZeroExtendingLoad()
2925 case Hexagon::L4_ploadrubt_abs: in isZeroExtendingLoad()
2926 case Hexagon::L4_ploadrubf_abs: in isZeroExtendingLoad()
2927 case Hexagon::L4_ploadrubtnew_abs: in isZeroExtendingLoad()
2928 case Hexagon::L4_ploadrubfnew_abs: in isZeroExtendingLoad()
2929 case Hexagon::L2_loadrubgp: in isZeroExtendingLoad()
2931 case Hexagon::L2_loadruh_io: in isZeroExtendingLoad()
2932 case Hexagon::L4_loadruh_ur: in isZeroExtendingLoad()
2933 case Hexagon::L4_loadruh_ap: in isZeroExtendingLoad()
2934 case Hexagon::L2_loadruh_pr: in isZeroExtendingLoad()
2935 case Hexagon::L2_loadruh_pbr: in isZeroExtendingLoad()
2936 case Hexagon::L2_loadruh_pi: in isZeroExtendingLoad()
2937 case Hexagon::L2_loadruh_pci: in isZeroExtendingLoad()
2938 case Hexagon::L2_loadruh_pcr: in isZeroExtendingLoad()
2939 case Hexagon::L4_loadruh_rr: in isZeroExtendingLoad()
2940 case Hexagon::L2_ploadruht_io: in isZeroExtendingLoad()
2941 case Hexagon::L2_ploadruht_pi: in isZeroExtendingLoad()
2942 case Hexagon::L2_ploadruhf_io: in isZeroExtendingLoad()
2943 case Hexagon::L2_ploadruhf_pi: in isZeroExtendingLoad()
2944 case Hexagon::L2_ploadruhtnew_io: in isZeroExtendingLoad()
2945 case Hexagon::L2_ploadruhfnew_io: in isZeroExtendingLoad()
2946 case Hexagon::L4_ploadruht_rr: in isZeroExtendingLoad()
2947 case Hexagon::L4_ploadruhf_rr: in isZeroExtendingLoad()
2948 case Hexagon::L4_ploadruhtnew_rr: in isZeroExtendingLoad()
2949 case Hexagon::L4_ploadruhfnew_rr: in isZeroExtendingLoad()
2950 case Hexagon::L2_ploadruhtnew_pi: in isZeroExtendingLoad()
2951 case Hexagon::L2_ploadruhfnew_pi: in isZeroExtendingLoad()
2952 case Hexagon::L4_ploadruht_abs: in isZeroExtendingLoad()
2953 case Hexagon::L4_ploadruhf_abs: in isZeroExtendingLoad()
2954 case Hexagon::L4_ploadruhtnew_abs: in isZeroExtendingLoad()
2955 case Hexagon::L4_ploadruhfnew_abs: in isZeroExtendingLoad()
2956 case Hexagon::L2_loadruhgp: in isZeroExtendingLoad()
2988 if (Second.mayStore() && First.getOpcode() == Hexagon::S2_allocframe) { in canExecuteInBundle()
2990 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29) in canExecuteInBundle()
3013 return Opc == Hexagon::PS_call_nr || Opc == Hexagon::PS_callr_nr; in doesNotReturn()
3029 if (Hexagon::getRegForm(MI.getOpcode()) >= 0) in hasNonExtEquivalent()
3039 NonExtOpcode = Hexagon::changeAddrMode_abs_io(MI.getOpcode()); in hasNonExtEquivalent()
3045 NonExtOpcode = Hexagon::changeAddrMode_io_rr(MI.getOpcode()); in hasNonExtEquivalent()
3048 NonExtOpcode = Hexagon::changeAddrMode_ur_rr(MI.getOpcode()); in hasNonExtEquivalent()
3061 return Hexagon::getRealHWInstr(MI.getOpcode(), in hasPseudoInstrPair()
3062 Hexagon::InstrType_Pseudo) >= 0; in hasPseudoInstrPair()
3143 case Hexagon::A4_addp_c: in predCanBeUsedAsDotNew()
3144 case Hexagon::A4_subp_c: in predCanBeUsedAsDotNew()
3145 case Hexagon::A4_tlbmatch: in predCanBeUsedAsDotNew()
3146 case Hexagon::A5_ACS: in predCanBeUsedAsDotNew()
3147 case Hexagon::F2_sfinvsqrta: in predCanBeUsedAsDotNew()
3148 case Hexagon::F2_sfrecipa: in predCanBeUsedAsDotNew()
3149 case Hexagon::J2_endloop0: in predCanBeUsedAsDotNew()
3150 case Hexagon::J2_endloop01: in predCanBeUsedAsDotNew()
3151 case Hexagon::J2_ploop1si: in predCanBeUsedAsDotNew()
3152 case Hexagon::J2_ploop1sr: in predCanBeUsedAsDotNew()
3153 case Hexagon::J2_ploop2si: in predCanBeUsedAsDotNew()
3154 case Hexagon::J2_ploop2sr: in predCanBeUsedAsDotNew()
3155 case Hexagon::J2_ploop3si: in predCanBeUsedAsDotNew()
3156 case Hexagon::J2_ploop3sr: in predCanBeUsedAsDotNew()
3157 case Hexagon::S2_cabacdecbin: in predCanBeUsedAsDotNew()
3158 case Hexagon::S2_storew_locked: in predCanBeUsedAsDotNew()
3159 case Hexagon::S4_stored_locked: in predCanBeUsedAsDotNew()
3166 return Opcode == Hexagon::J2_jumpt || in PredOpcodeHasJMP_c()
3167 Opcode == Hexagon::J2_jumptpt || in PredOpcodeHasJMP_c()
3168 Opcode == Hexagon::J2_jumpf || in PredOpcodeHasJMP_c()
3169 Opcode == Hexagon::J2_jumpfpt || in PredOpcodeHasJMP_c()
3170 Opcode == Hexagon::J2_jumptnew || in PredOpcodeHasJMP_c()
3171 Opcode == Hexagon::J2_jumpfnew || in PredOpcodeHasJMP_c()
3172 Opcode == Hexagon::J2_jumptnewpt || in PredOpcodeHasJMP_c()
3173 Opcode == Hexagon::J2_jumpfnewpt; in PredOpcodeHasJMP_c()
3339 case Hexagon::C2_cmpeq: in getCompoundCandidateGroup()
3340 case Hexagon::C2_cmpgt: in getCompoundCandidateGroup()
3341 case Hexagon::C2_cmpgtu: in getCompoundCandidateGroup()
3345 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3346 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3350 case Hexagon::C2_cmpeqi: in getCompoundCandidateGroup()
3351 case Hexagon::C2_cmpgti: in getCompoundCandidateGroup()
3352 case Hexagon::C2_cmpgtui: in getCompoundCandidateGroup()
3356 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3357 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3363 case Hexagon::A2_tfr: in getCompoundCandidateGroup()
3370 case Hexagon::A2_tfrsi: in getCompoundCandidateGroup()
3378 case Hexagon::S2_tstbit_i: in getCompoundCandidateGroup()
3381 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getCompoundCandidateGroup()
3382 (Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
3391 case Hexagon::J2_jumptnew: in getCompoundCandidateGroup()
3392 case Hexagon::J2_jumpfnew: in getCompoundCandidateGroup()
3393 case Hexagon::J2_jumptnewpt: in getCompoundCandidateGroup()
3394 case Hexagon::J2_jumpfnewpt: in getCompoundCandidateGroup()
3396 if (Hexagon::PredRegsRegClass.contains(Src1Reg) && in getCompoundCandidateGroup()
3397 (Hexagon::P0 == Src1Reg || Hexagon::P1 == Src1Reg)) in getCompoundCandidateGroup()
3404 case Hexagon::J2_jump: in getCompoundCandidateGroup()
3405 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in getCompoundCandidateGroup()
3406 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: in getCompoundCandidateGroup()
3418 if ((GA.getOpcode() != Hexagon::C2_cmpeqi) || in getCompoundOpcode()
3419 (GB.getOpcode() != Hexagon::J2_jumptnew)) in getCompoundOpcode()
3424 if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1) in getCompoundOpcode()
3432 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqn1_tp0_jump_nt in getCompoundOpcode()
3433 : Hexagon::J4_cmpeqn1_tp1_jump_nt; in getCompoundOpcode()
3436 return DestReg == Hexagon::P0 ? Hexagon::J4_cmpeqi_tp0_jump_nt in getCompoundOpcode()
3437 : Hexagon::J4_cmpeqi_tp1_jump_nt; in getCompoundOpcode()
3451 {Hexagon::A2_add, Hexagon::dup_A2_add}, in getDuplexOpcode()
3452 {Hexagon::A2_addi, Hexagon::dup_A2_addi}, in getDuplexOpcode()
3453 {Hexagon::A2_andir, Hexagon::dup_A2_andir}, in getDuplexOpcode()
3454 {Hexagon::A2_combineii, Hexagon::dup_A2_combineii}, in getDuplexOpcode()
3455 {Hexagon::A2_sxtb, Hexagon::dup_A2_sxtb}, in getDuplexOpcode()
3456 {Hexagon::A2_sxth, Hexagon::dup_A2_sxth}, in getDuplexOpcode()
3457 {Hexagon::A2_tfr, Hexagon::dup_A2_tfr}, in getDuplexOpcode()
3458 {Hexagon::A2_tfrsi, Hexagon::dup_A2_tfrsi}, in getDuplexOpcode()
3459 {Hexagon::A2_zxtb, Hexagon::dup_A2_zxtb}, in getDuplexOpcode()
3460 {Hexagon::A2_zxth, Hexagon::dup_A2_zxth}, in getDuplexOpcode()
3461 {Hexagon::A4_combineii, Hexagon::dup_A4_combineii}, in getDuplexOpcode()
3462 {Hexagon::A4_combineir, Hexagon::dup_A4_combineir}, in getDuplexOpcode()
3463 {Hexagon::A4_combineri, Hexagon::dup_A4_combineri}, in getDuplexOpcode()
3464 {Hexagon::C2_cmoveif, Hexagon::dup_C2_cmoveif}, in getDuplexOpcode()
3465 {Hexagon::C2_cmoveit, Hexagon::dup_C2_cmoveit}, in getDuplexOpcode()
3466 {Hexagon::C2_cmovenewif, Hexagon::dup_C2_cmovenewif}, in getDuplexOpcode()
3467 {Hexagon::C2_cmovenewit, Hexagon::dup_C2_cmovenewit}, in getDuplexOpcode()
3468 {Hexagon::C2_cmpeqi, Hexagon::dup_C2_cmpeqi}, in getDuplexOpcode()
3469 {Hexagon::L2_deallocframe, Hexagon::dup_L2_deallocframe}, in getDuplexOpcode()
3470 {Hexagon::L2_loadrb_io, Hexagon::dup_L2_loadrb_io}, in getDuplexOpcode()
3471 {Hexagon::L2_loadrd_io, Hexagon::dup_L2_loadrd_io}, in getDuplexOpcode()
3472 {Hexagon::L2_loadrh_io, Hexagon::dup_L2_loadrh_io}, in getDuplexOpcode()
3473 {Hexagon::L2_loadri_io, Hexagon::dup_L2_loadri_io}, in getDuplexOpcode()
3474 {Hexagon::L2_loadrub_io, Hexagon::dup_L2_loadrub_io}, in getDuplexOpcode()
3475 {Hexagon::L2_loadruh_io, Hexagon::dup_L2_loadruh_io}, in getDuplexOpcode()
3476 {Hexagon::S2_allocframe, Hexagon::dup_S2_allocframe}, in getDuplexOpcode()
3477 {Hexagon::S2_storerb_io, Hexagon::dup_S2_storerb_io}, in getDuplexOpcode()
3478 {Hexagon::S2_storerd_io, Hexagon::dup_S2_storerd_io}, in getDuplexOpcode()
3479 {Hexagon::S2_storerh_io, Hexagon::dup_S2_storerh_io}, in getDuplexOpcode()
3480 {Hexagon::S2_storeri_io, Hexagon::dup_S2_storeri_io}, in getDuplexOpcode()
3481 {Hexagon::S4_storeirb_io, Hexagon::dup_S4_storeirb_io}, in getDuplexOpcode()
3482 {Hexagon::S4_storeiri_io, Hexagon::dup_S4_storeiri_io}, in getDuplexOpcode()
3499 enum Hexagon::PredSense inPredSense; in getCondOpcode()
3500 inPredSense = invertPredicate ? Hexagon::PredSense_false : in getCondOpcode()
3501 Hexagon::PredSense_true; in getCondOpcode()
3502 int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense); in getCondOpcode()
3513 case Hexagon::V6_vL32b_pi: in getDotCurOp()
3514 return Hexagon::V6_vL32b_cur_pi; in getDotCurOp()
3515 case Hexagon::V6_vL32b_ai: in getDotCurOp()
3516 return Hexagon::V6_vL32b_cur_ai; in getDotCurOp()
3517 case Hexagon::V6_vL32b_nt_pi: in getDotCurOp()
3518 return Hexagon::V6_vL32b_nt_cur_pi; in getDotCurOp()
3519 case Hexagon::V6_vL32b_nt_ai: in getDotCurOp()
3520 return Hexagon::V6_vL32b_nt_cur_ai; in getDotCurOp()
3529 case Hexagon::V6_vL32b_cur_pi: in getNonDotCurOp()
3530 return Hexagon::V6_vL32b_pi; in getNonDotCurOp()
3531 case Hexagon::V6_vL32b_cur_ai: in getNonDotCurOp()
3532 return Hexagon::V6_vL32b_ai; in getNonDotCurOp()
3533 case Hexagon::V6_vL32b_nt_cur_pi: in getNonDotCurOp()
3534 return Hexagon::V6_vL32b_nt_pi; in getNonDotCurOp()
3535 case Hexagon::V6_vL32b_nt_cur_ai: in getNonDotCurOp()
3536 return Hexagon::V6_vL32b_nt_ai; in getNonDotCurOp()
3624 int NVOpcode = Hexagon::getNewValueOpcode(MI.getOpcode()); in getDotNewOp()
3632 case Hexagon::S4_storerb_ur: in getDotNewOp()
3633 return Hexagon::S4_storerbnew_ur; in getDotNewOp()
3635 case Hexagon::S2_storerb_pci: in getDotNewOp()
3636 return Hexagon::S2_storerb_pci; in getDotNewOp()
3638 case Hexagon::S2_storeri_pci: in getDotNewOp()
3639 return Hexagon::S2_storeri_pci; in getDotNewOp()
3641 case Hexagon::S2_storerh_pci: in getDotNewOp()
3642 return Hexagon::S2_storerh_pci; in getDotNewOp()
3644 case Hexagon::S2_storerd_pci: in getDotNewOp()
3645 return Hexagon::S2_storerd_pci; in getDotNewOp()
3647 case Hexagon::S2_storerf_pci: in getDotNewOp()
3648 return Hexagon::S2_storerf_pci; in getDotNewOp()
3650 case Hexagon::V6_vS32b_ai: in getDotNewOp()
3651 return Hexagon::V6_vS32b_new_ai; in getDotNewOp()
3653 case Hexagon::V6_vS32b_pi: in getDotNewOp()
3654 return Hexagon::V6_vS32b_new_pi; in getDotNewOp()
3739 case Hexagon::J2_jumpt: in getDotNewPredJumpOp()
3740 return Taken ? Hexagon::J2_jumptnewpt : Hexagon::J2_jumptnew; in getDotNewPredJumpOp()
3741 case Hexagon::J2_jumpf: in getDotNewPredJumpOp()
3742 return Taken ? Hexagon::J2_jumpfnewpt : Hexagon::J2_jumpfnew; in getDotNewPredJumpOp()
3754 case Hexagon::J2_jumpt: in getDotNewPredOp()
3755 case Hexagon::J2_jumpf: in getDotNewPredOp()
3759 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); in getDotNewPredOp()
3768 NewOp = Hexagon::getPredOldOpcode(NewOp); in getDotOldOp()
3772 if (!Subtarget.getFeatureBits()[Hexagon::ArchV60]) { in getDotOldOp()
3774 case Hexagon::J2_jumptpt: in getDotOldOp()
3775 NewOp = Hexagon::J2_jumpt; in getDotOldOp()
3777 case Hexagon::J2_jumpfpt: in getDotOldOp()
3778 NewOp = Hexagon::J2_jumpf; in getDotOldOp()
3780 case Hexagon::J2_jumprtpt: in getDotOldOp()
3781 NewOp = Hexagon::J2_jumprt; in getDotOldOp()
3783 case Hexagon::J2_jumprfpt: in getDotOldOp()
3784 NewOp = Hexagon::J2_jumprf; in getDotOldOp()
3793 NewOp = Hexagon::getNonNVStore(NewOp); in getDotOldOp()
3802 case Hexagon::J2_jumpfpt: in getDotOldOp()
3803 return Hexagon::J2_jumpf; in getDotOldOp()
3804 case Hexagon::J2_jumptpt: in getDotOldOp()
3805 return Hexagon::J2_jumpt; in getDotOldOp()
3806 case Hexagon::J2_jumprfpt: in getDotOldOp()
3807 return Hexagon::J2_jumprf; in getDotOldOp()
3808 case Hexagon::J2_jumprtpt: in getDotOldOp()
3809 return Hexagon::J2_jumprt; in getDotOldOp()
3829 case Hexagon::L2_loadri_io: in getDuplexCandidateGroup()
3830 case Hexagon::dup_L2_loadri_io: in getDuplexCandidateGroup()
3836 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3848 case Hexagon::L2_loadrub_io: in getDuplexCandidateGroup()
3849 case Hexagon::dup_L2_loadrub_io: in getDuplexCandidateGroup()
3867 case Hexagon::L2_loadrh_io: in getDuplexCandidateGroup()
3868 case Hexagon::L2_loadruh_io: in getDuplexCandidateGroup()
3869 case Hexagon::dup_L2_loadrh_io: in getDuplexCandidateGroup()
3870 case Hexagon::dup_L2_loadruh_io: in getDuplexCandidateGroup()
3879 case Hexagon::L2_loadrb_io: in getDuplexCandidateGroup()
3880 case Hexagon::dup_L2_loadrb_io: in getDuplexCandidateGroup()
3889 case Hexagon::L2_loadrd_io: in getDuplexCandidateGroup()
3890 case Hexagon::dup_L2_loadrd_io: in getDuplexCandidateGroup()
3895 Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3903 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4: in getDuplexCandidateGroup()
3904 case Hexagon::RESTORE_DEALLOC_RET_JMP_V4_PIC: in getDuplexCandidateGroup()
3905 case Hexagon::L4_return: in getDuplexCandidateGroup()
3906 case Hexagon::L2_deallocframe: in getDuplexCandidateGroup()
3907 case Hexagon::dup_L2_deallocframe: in getDuplexCandidateGroup()
3909 case Hexagon::EH_RETURN_JMPR: in getDuplexCandidateGroup()
3910 case Hexagon::PS_jmpret: in getDuplexCandidateGroup()
3911 case Hexagon::SL2_jumpr31: in getDuplexCandidateGroup()
3915 if (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg)) in getDuplexCandidateGroup()
3918 case Hexagon::PS_jmprett: in getDuplexCandidateGroup()
3919 case Hexagon::PS_jmpretf: in getDuplexCandidateGroup()
3920 case Hexagon::PS_jmprettnewpt: in getDuplexCandidateGroup()
3921 case Hexagon::PS_jmpretfnewpt: in getDuplexCandidateGroup()
3922 case Hexagon::PS_jmprettnew: in getDuplexCandidateGroup()
3923 case Hexagon::PS_jmpretfnew: in getDuplexCandidateGroup()
3924 case Hexagon::SL2_jumpr31_t: in getDuplexCandidateGroup()
3925 case Hexagon::SL2_jumpr31_f: in getDuplexCandidateGroup()
3926 case Hexagon::SL2_jumpr31_tnew: in getDuplexCandidateGroup()
3927 case Hexagon::SL2_jumpr31_fnew: in getDuplexCandidateGroup()
3931 if ((Hexagon::PredRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
3932 (Hexagon::P0 == SrcReg)) && in getDuplexCandidateGroup()
3933 (Hexagon::IntRegsRegClass.contains(DstReg) && (Hexagon::R31 == DstReg))) in getDuplexCandidateGroup()
3936 case Hexagon::L4_return_t: in getDuplexCandidateGroup()
3937 case Hexagon::L4_return_f: in getDuplexCandidateGroup()
3938 case Hexagon::L4_return_tnew_pnt: in getDuplexCandidateGroup()
3939 case Hexagon::L4_return_fnew_pnt: in getDuplexCandidateGroup()
3940 case Hexagon::L4_return_tnew_pt: in getDuplexCandidateGroup()
3941 case Hexagon::L4_return_fnew_pt: in getDuplexCandidateGroup()
3944 if (Hexagon::PredRegsRegClass.contains(SrcReg) && (Hexagon::P0 == SrcReg)) in getDuplexCandidateGroup()
3952 case Hexagon::S2_storeri_io: in getDuplexCandidateGroup()
3953 case Hexagon::dup_S2_storeri_io: in getDuplexCandidateGroup()
3958 if (Hexagon::IntRegsRegClass.contains(Src1Reg) && in getDuplexCandidateGroup()
3969 case Hexagon::S2_storerb_io: in getDuplexCandidateGroup()
3970 case Hexagon::dup_S2_storerb_io: in getDuplexCandidateGroup()
3987 case Hexagon::S2_storerh_io: in getDuplexCandidateGroup()
3988 case Hexagon::dup_S2_storerh_io: in getDuplexCandidateGroup()
3997 case Hexagon::S2_storerd_io: in getDuplexCandidateGroup()
3998 case Hexagon::dup_S2_storerd_io: in getDuplexCandidateGroup()
4003 Hexagon::IntRegsRegClass.contains(Src1Reg) && in getDuplexCandidateGroup()
4008 case Hexagon::S4_storeiri_io: in getDuplexCandidateGroup()
4009 case Hexagon::dup_S4_storeiri_io: in getDuplexCandidateGroup()
4017 case Hexagon::S4_storeirb_io: in getDuplexCandidateGroup()
4018 case Hexagon::dup_S4_storeirb_io: in getDuplexCandidateGroup()
4026 case Hexagon::S2_allocframe: in getDuplexCandidateGroup()
4027 case Hexagon::dup_S2_allocframe: in getDuplexCandidateGroup()
4050 case Hexagon::A2_addi: in getDuplexCandidateGroup()
4051 case Hexagon::dup_A2_addi: in getDuplexCandidateGroup()
4056 if (Hexagon::IntRegsRegClass.contains(SrcReg) && in getDuplexCandidateGroup()
4072 case Hexagon::A2_add: in getDuplexCandidateGroup()
4073 case Hexagon::dup_A2_add: in getDuplexCandidateGroup()
4082 case Hexagon::A2_andir: in getDuplexCandidateGroup()
4083 case Hexagon::dup_A2_andir: in getDuplexCandidateGroup()
4095 case Hexagon::A2_tfr: in getDuplexCandidateGroup()
4096 case Hexagon::dup_A2_tfr: in getDuplexCandidateGroup()
4103 case Hexagon::A2_tfrsi: in getDuplexCandidateGroup()
4104 case Hexagon::dup_A2_tfrsi: in getDuplexCandidateGroup()
4113 case Hexagon::C2_cmoveit: in getDuplexCandidateGroup()
4114 case Hexagon::C2_cmovenewit: in getDuplexCandidateGroup()
4115 case Hexagon::C2_cmoveif: in getDuplexCandidateGroup()
4116 case Hexagon::C2_cmovenewif: in getDuplexCandidateGroup()
4117 case Hexagon::dup_C2_cmoveit: in getDuplexCandidateGroup()
4118 case Hexagon::dup_C2_cmovenewit: in getDuplexCandidateGroup()
4119 case Hexagon::dup_C2_cmoveif: in getDuplexCandidateGroup()
4120 case Hexagon::dup_C2_cmovenewif: in getDuplexCandidateGroup()
4127 Hexagon::PredRegsRegClass.contains(SrcReg) && Hexagon::P0 == SrcReg && in getDuplexCandidateGroup()
4131 case Hexagon::C2_cmpeqi: in getDuplexCandidateGroup()
4132 case Hexagon::dup_C2_cmpeqi: in getDuplexCandidateGroup()
4136 if (Hexagon::PredRegsRegClass.contains(DstReg) && in getDuplexCandidateGroup()
4137 Hexagon::P0 == DstReg && isIntRegForSubInst(SrcReg) && in getDuplexCandidateGroup()
4141 case Hexagon::A2_combineii: in getDuplexCandidateGroup()
4142 case Hexagon::A4_combineii: in getDuplexCandidateGroup()
4143 case Hexagon::dup_A2_combineii: in getDuplexCandidateGroup()
4144 case Hexagon::dup_A4_combineii: in getDuplexCandidateGroup()
4156 case Hexagon::A4_combineri: in getDuplexCandidateGroup()
4157 case Hexagon::dup_A4_combineri: in getDuplexCandidateGroup()
4167 case Hexagon::A4_combineir: in getDuplexCandidateGroup()
4168 case Hexagon::dup_A4_combineir: in getDuplexCandidateGroup()
4177 case Hexagon::A2_sxtb: in getDuplexCandidateGroup()
4178 case Hexagon::A2_sxth: in getDuplexCandidateGroup()
4179 case Hexagon::A2_zxtb: in getDuplexCandidateGroup()
4180 case Hexagon::A2_zxth: in getDuplexCandidateGroup()
4181 case Hexagon::dup_A2_sxtb: in getDuplexCandidateGroup()
4182 case Hexagon::dup_A2_sxth: in getDuplexCandidateGroup()
4183 case Hexagon::dup_A2_zxtb: in getDuplexCandidateGroup()
4184 case Hexagon::dup_A2_zxth: in getDuplexCandidateGroup()
4197 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Real); in getEquivalentHWInstr()
4277 InvPredOpcode = isPredicatedTrue(Opc) ? Hexagon::getFalsePredOpcode(Opc) in getInvertedPredicatedOpcode()
4278 : Hexagon::getTruePredOpcode(Opc); in getInvertedPredicatedOpcode()
4302 case Hexagon::L2_loadrbgp: in isAddrModeWithOffset()
4303 case Hexagon::L2_loadrdgp: in isAddrModeWithOffset()
4304 case Hexagon::L2_loadrhgp: in isAddrModeWithOffset()
4305 case Hexagon::L2_loadrigp: in isAddrModeWithOffset()
4306 case Hexagon::L2_loadrubgp: in isAddrModeWithOffset()
4307 case Hexagon::L2_loadruhgp: in isAddrModeWithOffset()
4308 case Hexagon::S2_storerbgp: in isAddrModeWithOffset()
4309 case Hexagon::S2_storerbnewgp: in isAddrModeWithOffset()
4310 case Hexagon::S2_storerhgp: in isAddrModeWithOffset()
4311 case Hexagon::S2_storerhnewgp: in isAddrModeWithOffset()
4312 case Hexagon::S2_storerigp: in isAddrModeWithOffset()
4313 case Hexagon::S2_storerinewgp: in isAddrModeWithOffset()
4314 case Hexagon::S2_storerdgp: in isAddrModeWithOffset()
4315 case Hexagon::S2_storerfgp: in isAddrModeWithOffset()
4333 if (MI.getOpcode() == Hexagon::A4_ext) in isPureSlot0()
4396 return HRI.getSpillSize(Hexagon::HvxVRRegClass); in getMemAccessSize()
4420 short NonExtOpcode = Hexagon::getRegForm(MI.getOpcode()); in getNonExtOpcode()
4428 return Hexagon::changeAddrMode_abs_io(MI.getOpcode()); in getNonExtOpcode()
4430 return Hexagon::changeAddrMode_io_rr(MI.getOpcode()); in getNonExtOpcode()
4432 return Hexagon::changeAddrMode_ur_rr(MI.getOpcode()); in getNonExtOpcode()
4462 return Hexagon::getRealHWInstr(MI.getOpcode(), Hexagon::InstrType_Pseudo); in getPseudoInstrPair()
4466 return Hexagon::getRegForm(MI.getOpcode()); in getRegForm()
4487 if (BranchRelaxAsmLarge && MI.getOpcode() == Hexagon::INLINEASM) { in getSize()
4577 insn < Hexagon::INSTRUCTION_LIST_END; ++insn) { in genAllInsnTimingClasses()
4600 PredRevOpcode = Hexagon::notTakenBranchPrediction(Opcode); in reversePrediction()
4602 PredRevOpcode = Hexagon::takenBranchPrediction(Opcode); in reversePrediction()
4631 return Opc >= 0 ? Hexagon::changeAddrMode_abs_io(Opc) : Opc; in changeAddrMode_abs_io()
4635 return Opc >= 0 ? Hexagon::changeAddrMode_io_abs(Opc) : Opc; in changeAddrMode_io_abs()
4639 return Opc >= 0 ? Hexagon::changeAddrMode_io_pi(Opc) : Opc; in changeAddrMode_io_pi()
4643 return Opc >= 0 ? Hexagon::changeAddrMode_io_rr(Opc) : Opc; in changeAddrMode_io_rr()
4647 return Opc >= 0 ? Hexagon::changeAddrMode_pi_io(Opc) : Opc; in changeAddrMode_pi_io()
4651 return Opc >= 0 ? Hexagon::changeAddrMode_rr_io(Opc) : Opc; in changeAddrMode_rr_io()
4655 return Opc >= 0 ? Hexagon::changeAddrMode_rr_ur(Opc) : Opc; in changeAddrMode_rr_ur()
4659 return Opc >= 0 ? Hexagon::changeAddrMode_ur_rr(Opc) : Opc; in changeAddrMode_ur_rr()