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Lines Matching refs:MachineInstr

34 class MachineInstr;  variable
57   unsigned isLoadFromStackSlot(const MachineInstr &MI,
65   unsigned isStoreToStackSlot(const MachineInstr &MI,
72       const MachineInstr &MI,
79       const MachineInstr &MI,
204   bool expandPostRAPseudo(MachineInstr &MI) const override;
208       const MachineInstr &LdSt,
223   bool isPredicated(const MachineInstr &MI) const override;
226   bool isPostIncrement(const MachineInstr &MI) const override;
230   bool PredicateInstruction(MachineInstr &MI,
241   bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
247   bool isPredicable(const MachineInstr &MI) const override;
251   bool isSchedulingBoundary(const MachineInstr &MI,
272   bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
279                            const MachineInstr &MI,
291   areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
292                                   const MachineInstr &MIb) const override;
296   bool getBaseAndOffsetPosition(const MachineInstr &MI, unsigned &BasePos,
300   bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
311                         const MachineInstr &DefMI, unsigned DefIdx,
312                         const MachineInstr &UseMI,
336   bool isTailCall(const MachineInstr &MI) const override;
341   MachineInstr *findLoopInstr(MachineBasicBlock *BB, unsigned EndLoopOp,
345   bool isAbsoluteSet(const MachineInstr &MI) const;
346   bool isAccumulator(const MachineInstr &MI) const;
347   bool isAddrModeWithOffset(const MachineInstr &MI) const;
348   bool isBaseImmOffset(const MachineInstr &MI) const;
349   bool isComplex(const MachineInstr &MI) const;
350   bool isCompoundBranchInstr(const MachineInstr &MI) const;
351   bool isConstExtended(const MachineInstr &MI) const;
352   bool isDeallocRet(const MachineInstr &MI) const;
353   bool isDependent(const MachineInstr &ProdMI,
354                    const MachineInstr &ConsMI) const;
355   bool isDotCurInst(const MachineInstr &MI) const;
356   bool isDotNewInst(const MachineInstr &MI) const;
357   bool isDuplexPair(const MachineInstr &MIa, const MachineInstr &MIb) const;
358   bool isEarlySourceInstr(const MachineInstr &MI) const;
361   bool isExtendable(const MachineInstr &MI) const;
362   bool isExtended(const MachineInstr &MI) const;
363   bool isFloat(const MachineInstr &MI) const;
364   bool isHVXMemWithAIndirect(const MachineInstr &I,
365                              const MachineInstr &J) const;
366   bool isIndirectCall(const MachineInstr &MI) const;
367   bool isIndirectL4Return(const MachineInstr &MI) const;
368   bool isJumpR(const MachineInstr &MI) const;
369   bool isJumpWithinBranchRange(const MachineInstr &MI, unsigned offset) const;
370   bool isLateInstrFeedsEarlyInstr(const MachineInstr &LRMI,
371                                   const MachineInstr &ESMI) const;
372   bool isLateResultInstr(const MachineInstr &MI) const;
373   bool isLateSourceInstr(const MachineInstr &MI) const;
374   bool isLoopN(const MachineInstr &MI) const;
375   bool isMemOp(const MachineInstr &MI) const;
376   bool isNewValue(const MachineInstr &MI) const;
378   bool isNewValueInst(const MachineInstr &MI) const;
379   bool isNewValueJump(const MachineInstr &MI) const;
381   bool isNewValueStore(const MachineInstr &MI) const;
383   bool isOperandExtended(const MachineInstr &MI, unsigned OperandNum) const;
384   bool isPredicatedNew(const MachineInstr &MI) const;
386   bool isPredicatedTrue(const MachineInstr &MI) const;
391   bool isPureSlot0(const MachineInstr &MI) const;
392   bool isRestrictNoSlot1Store(const MachineInstr &MI) const;
393   bool isSaveCalleeSavedRegsCall(const MachineInstr &MI) const;
394   bool isSignExtendingLoad(const MachineInstr &MI) const;
395   bool isSolo(const MachineInstr &MI) const;
396   bool isSpillPredRegOp(const MachineInstr &MI) const;
397   bool isTC1(const MachineInstr &MI) const;
398   bool isTC2(const MachineInstr &MI) const;
399   bool isTC2Early(const MachineInstr &MI) const;
400   bool isTC4x(const MachineInstr &MI) const;
401   bool isToBeScheduledASAP(const MachineInstr &MI1,
402                            const MachineInstr &MI2) const;
403   bool isHVXVec(const MachineInstr &MI) const;
407   bool isVecAcc(const MachineInstr &MI) const;
408   bool isVecALU(const MachineInstr &MI) const;
409   bool isVecUsableNextPacket(const MachineInstr &ProdMI,
410                              const MachineInstr &ConsMI) const;
411   bool isZeroExtendingLoad(const MachineInstr &MI) const;
413   bool addLatencyToSchedule(const MachineInstr &MI1,
414                             const MachineInstr &MI2) const;
415   bool canExecuteInBundle(const MachineInstr &First,
416                           const MachineInstr &Second) const;
417   bool doesNotReturn(const MachineInstr &CallMI) const;
419   bool hasNonExtEquivalent(const MachineInstr &MI) const;
420   bool hasPseudoInstrPair(const MachineInstr &MI) const;
422   bool mayBeCurLoad(const MachineInstr &MI) const;
423   bool mayBeNewStore(const MachineInstr &MI) const;
424   bool producesStall(const MachineInstr &ProdMI,
425                      const MachineInstr &ConsMI) const;
426   bool producesStall(const MachineInstr &MI,
428   bool predCanBeUsedAsDotNew(const MachineInstr &MI, unsigned PredReg) const;
432   unsigned getAddrMode(const MachineInstr &MI) const;
433   MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
435   SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
436   unsigned getCExtOpNum(const MachineInstr &MI) const;
438   getCompoundCandidateGroup(const MachineInstr &MI) const;
439   unsigned getCompoundOpcode(const MachineInstr &GA,
440                              const MachineInstr &GB) const;
441   int getDuplexOpcode(const MachineInstr &MI, bool ForBigCore = true) const;
443   int getDotCurOp(const MachineInstr &MI) const;
444   int getNonDotCurOp(const MachineInstr &MI) const;
445   int getDotNewOp(const MachineInstr &MI) const;
446   int getDotNewPredJumpOp(const MachineInstr &MI,
448   int getDotNewPredOp(const MachineInstr &MI,
450   int getDotOldOp(const MachineInstr &MI) const;
451   HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr &MI)
453   short getEquivalentHWInstr(const MachineInstr &MI) const;
455                                       const MachineInstr &MI) const;
458   int getMaxValue(const MachineInstr &MI) const;
459   unsigned getMemAccessSize(const MachineInstr &MI) const;
460   int getMinValue(const MachineInstr &MI) const;
461   short getNonExtOpcode(const MachineInstr &MI) const;
464   short getPseudoInstrPair(const MachineInstr &MI) const;
465   short getRegForm(const MachineInstr &MI) const;
466   unsigned getSize(const MachineInstr &MI) const;
467   uint64_t getType(const MachineInstr &MI) const;
468   InstrStage::FuncUnits getUnits(const MachineInstr &MI) const;
470   MachineBasicBlock::instr_iterator expandVGatherPseudo(MachineInstr &MI) const;
477   void immediateExtend(MachineInstr &MI) const;
478   bool invertAndChangeJumpTarget(MachineInstr &MI,
481   bool reversePredSense(MachineInstr &MI) const;
486   bool getBundleNoShuf(const MachineInstr &MIB) const;
508   short changeAddrMode_abs_io(const MachineInstr &MI) const {  in changeAddrMode_abs_io()
511   short changeAddrMode_io_abs(const MachineInstr &MI) const {  in changeAddrMode_io_abs()
514   short changeAddrMode_io_rr(const MachineInstr &MI) const {  in changeAddrMode_io_rr()
517   short changeAddrMode_rr_io(const MachineInstr &MI) const {  in changeAddrMode_rr_io()
520   short changeAddrMode_rr_ur(const MachineInstr &MI) const {  in changeAddrMode_rr_ur()
523   short changeAddrMode_ur_rr(const MachineInstr &MI) const {  in changeAddrMode_ur_rr()