Lines Matching refs:IntID

11 class T_R_pat <InstHexagon MI, Intrinsic IntID>
12   : Pat <(IntID I32:$Rs),
15 class T_RR_pat <InstHexagon MI, Intrinsic IntID>
16   : Pat <(IntID I32:$Rs, I32:$Rt),
19 class T_RP_pat <InstHexagon MI, Intrinsic IntID>
20   : Pat <(IntID I32:$Rs, I64:$Rt),
143 class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
145   : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
186 class T_stb_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Val>
187   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru),
196 class T_stc_pat <InstHexagon MI, Intrinsic IntID, PatLeaf Imm, PatLeaf Val>
197   : Pat<(IntID I32:$Rs, Val:$Rt, I32:$Ru, Imm:$s),
206 multiclass MaskedStore <InstHexagon MI, Intrinsic IntID> {
207   def : Pat<(IntID HvxQR:$src1, IntRegs:$src2, HvxVR:$src3),
211   def : Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2,
288 multiclass T_VI_pat <InstHexagon MI, Intrinsic IntID> {
289   def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
293   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_0ImmPred:$src2),
298 multiclass T_VI_inv_pat <InstHexagon MI, Intrinsic IntID> {
299   def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
304   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, u3_128_ImmPred:$src2),
309 multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
310   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_0ImmPred:$src3),
314   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
321 multiclass T_VVI_inv_pat <InstHexagon MI, Intrinsic IntID> {
322   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, u3_64_ImmPred:$src3),
327   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
334 multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
335   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
339   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,