Lines Matching refs:IntID

9 multiclass T_VR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
10   def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
16 multiclass T_VVL_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
17   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
19   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
24 multiclass T_VV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
25   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
27   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2),
31 multiclass T_WW_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
32   def: Pat<(IntID HvxWR:$src1, HvxWR:$src2),
34   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2),
38 multiclass T_WVV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
39   def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3),
41   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,
46 multiclass T_WR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
47   def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
49   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, IntRegs:$src2),
53 multiclass T_WWR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
54   def: Pat<(IntID HvxWR:$src1, HvxWR:$src2, IntRegs:$src3),
56   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxWR:$src2,
61 multiclass T_VVR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
62   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegs:$src3),
64   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
69 multiclass T_ZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
70   def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
72   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, IntRegs:$src2),
76 multiclass T_VZR_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
77   def: Pat<(IntID HvxVR:$src1, HvxQR:$src2, IntRegs:$src3),
79   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxQR:$src2,
84 multiclass T_ZV_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
85   def: Pat<(IntID HvxQR:$src1, HvxVR:$src2),
87   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxVR:$src2),
91 multiclass T_R_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
92   def: Pat<(IntID IntRegs:$src1),
94   def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
98 multiclass T_ZZ_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
99   def: Pat<(IntID HvxQR:$src1, HvxQR:$src2),
101   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxQR:$src1, HvxQR:$src2),
105 multiclass T_VVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
106   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, imm:$src3),
108   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
113 multiclass T_VVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
114   def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
116   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
121 multiclass T_WVVI_HVX_gen_pat <InstHexagon MI, Intrinsic IntID> {
122   def: Pat<(IntID HvxWR:$src1, HvxVR:$src2, HvxVR:$src3, imm:$src4),
124   def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxWR:$src1, HvxVR:$src2,