Lines Matching refs:Rd
49 // Rd - 64-bit registers.
50 class Rd<bits<5> num, string n, list<Register> subregs,
112 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
113 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
114 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
115 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
116 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
117 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
118 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
119 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
120 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
121 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
122 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
123 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
124 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
125 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
126 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
127 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>;
207 def W0 : Rd< 0, "v1:0", [V0, V1, VF0]>, DwarfRegNum<[99]>;
208 def W1 : Rd< 2, "v3:2", [V2, V3, VF1]>, DwarfRegNum<[101]>;
209 def W2 : Rd< 4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>;
210 def W3 : Rd< 6, "v7:6", [V6, V7, VF3]>, DwarfRegNum<[105]>;
211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>;
212 def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>;
213 def W6 : Rd<12, "v13:12", [V12, V13, VF6]>, DwarfRegNum<[111]>;
214 def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>;
215 def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>;
216 def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>;
217 def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>;
218 def W11 : Rd<22, "v23:22", [V22, V23, VF11]>, DwarfRegNum<[121]>;
219 def W12 : Rd<24, "v25:24", [V24, V25, VF12]>, DwarfRegNum<[123]>;
220 def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>;
221 def W14 : Rd<28, "v29:28", [V28, V29, VF14]>, DwarfRegNum<[127]>;
222 def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>;
227 def WR0 : Rd< 1, "v0:1", [V0, V1, VFR0]>, DwarfRegNum<[161]>;
228 def WR1 : Rd< 3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>;
229 def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>;
230 def WR3 : Rd< 7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>;
231 def WR4 : Rd< 9, "v8:9", [V8, V9, VFR4]>, DwarfRegNum<[165]>;
232 def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>;
233 def WR6 : Rd<13, "v12:13", [V12, V13, VFR6]>, DwarfRegNum<[167]>;
234 def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>;
235 def WR8 : Rd<17, "v16:17", [V16, V17, VFR8]>, DwarfRegNum<[169]>;
236 def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>;
237 def WR10: Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>;
238 def WR11: Rd<23, "v22:23", [V22, V23, VFR11]>, DwarfRegNum<[172]>;
239 def WR12: Rd<25, "v24:25", [V24, V25, VFR12]>, DwarfRegNum<[173]>;
240 def WR13: Rd<27, "v26:27", [V26, V27, VFR13]>, DwarfRegNum<[174]>;
241 def WR14: Rd<29, "v28:29", [V28, V29, VFR14]>, DwarfRegNum<[175]>;
242 def WR15: Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>;
247 def VQ0 : Rd< 0, "v3:0", [W0, W1]>, DwarfRegNum<[252]>;
248 def VQ1 : Rd< 4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>;
249 def VQ2 : Rd< 8, "v11:8", [W4, W5]>, DwarfRegNum<[254]>;
250 def VQ3 : Rd<12, "v15:12", [W6, W7]>, DwarfRegNum<[255]>;
251 def VQ4 : Rd<16, "v19:16", [W8, W9]>, DwarfRegNum<[256]>;
252 def VQ5 : Rd<20, "v23:20", [W10, W11]>, DwarfRegNum<[257]>;
253 def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>;
254 def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>;