73 static bool isVecReg(unsigned Reg) {  in isVecReg()  argument
74   return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) ||  in isVecReg()
75          (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) ||  in isVecReg()
76          (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) ||  in isVecReg()
77          (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3);  in isVecReg()
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg,  in addAsmInstr()  argument
100   std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg);  in addAsmInstr()
108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) {  in getInstrVecReg()  argument
112     Reg = MI.getOperand(0).getReg();  in getInstrVecReg()
113     if (isVecReg(Reg))  in getInstrVecReg()
118     Reg = MI.getOperand(2).getReg();  in getInstrVecReg()
119     if (isVecReg(Reg))  in getInstrVecReg()
124     Reg = MI.getOperand(3).getReg();  in getInstrVecReg()
125     if (isVecReg(Reg))  in getInstrVecReg()
144           unsigned Reg = 0;  in runOnMachineFunction()  local
145           if (getInstrVecReg(*MII, Reg)) {  in runOnMachineFunction()
152         unsigned Reg = 0;  in runOnMachineFunction()  local
153         if (getInstrVecReg(MI, Reg)) {  in runOnMachineFunction()
168     unsigned Reg = 0;  in runOnMachineFunction()  local
169     if (!getInstrVecReg(*I, Reg))  in runOnMachineFunction()
183     if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) {  in runOnMachineFunction()
184       LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n');  in runOnMachineFunction()
185       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);  in runOnMachineFunction()
186     } else if (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) {  in runOnMachineFunction()
187       LLVM_DEBUG(dbgs() << "adding dump for W" << Reg - Hexagon::W0 << '\n');  in runOnMachineFunction()
188       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1,  in runOnMachineFunction()
190       addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2,  in runOnMachineFunction()
192     } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) {  in runOnMachineFunction()
193       LLVM_DEBUG(dbgs() << "adding dump for Q" << Reg - Hexagon::Q0 << '\n');  in runOnMachineFunction()
194       addAsmInstr(MBB, Reg, MII, DL, QII, Fn);  in runOnMachineFunction()