3365   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadSingleImmToGPR()  local
3370   return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,  in expandLoadSingleImmToGPR()
3382   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadSingleImmToFPR()  local
3400     TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadSingleImmToFPR()
3423   TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),  in expandLoadSingleImmToFPR()
3436   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadDoubleImmToGPR()  local
3443       if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,  in expandLoadDoubleImmToGPR()
3447       if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,  in expandLoadDoubleImmToGPR()
3451       if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,  in expandLoadDoubleImmToGPR()
3485     TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);  in expandLoadDoubleImmToGPR()
3487     TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);  in expandLoadDoubleImmToGPR()
3488     TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);  in expandLoadDoubleImmToGPR()
3501   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadDoubleImmToFPR()  local
3520       TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3530       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3531       TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3533       TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3534       TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);  in expandLoadDoubleImmToFPR()
3560   TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,  in expandLoadDoubleImmToFPR()
4342   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandTrunc()  local
4359                 FirstReg, SecondReg, IDLoc, STI);  in expandTrunc()
4367               FirstReg, SecondReg, IDLoc, STI);  in expandTrunc()
5284   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandLoadStoreDMacro()  local
5285   unsigned SecondReg = nextReg(FirstReg);  in expandLoadStoreDMacro()
5290   warnIfRegIndexIsAT(FirstReg, IDLoc);  in expandLoadStoreDMacro()
5304   if (FirstReg != BaseReg || !IsLoad) {  in expandLoadStoreDMacro()
5305     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5309     TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandLoadStoreDMacro()
5331   unsigned FirstReg = Inst.getOperand(0).getReg();  in expandStoreDM1Macro()  local
5332   unsigned SecondReg = nextReg(FirstReg);  in expandStoreDM1Macro()
5337   warnIfRegIndexIsAT(FirstReg, IDLoc);  in expandStoreDM1Macro()
5350     std::swap(FirstReg, SecondReg);  in expandStoreDM1Macro()
5352   TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI);  in expandStoreDM1Macro()