Lines Matching refs:IDLoc
175 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
222 MacroExpanderResultTy tryExpandInstruction(MCInst &Inst, SMLoc IDLoc,
226 bool expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
230 bool Is32BitImm, bool IsAddress, SMLoc IDLoc,
234 unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
237 bool emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, MCSymbol *Sym);
239 bool expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc,
242 bool expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
244 bool expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
246 bool expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
248 bool expandLoadDoubleImmToFPR(MCInst &Inst, bool Is64FPU, SMLoc IDLoc,
253 SMLoc IDLoc, MCStreamer &Out,
256 bool expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
259 void expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
261 void expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
264 bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
267 bool expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
270 bool expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
273 bool expandCondBranches(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
276 bool expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
280 bool expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, SMLoc IDLoc,
283 bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out,
286 bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
289 bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
292 bool expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
295 bool expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
298 bool expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
301 bool expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
304 bool expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
307 bool expandRotation(MCInst &Inst, SMLoc IDLoc,
309 bool expandRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
311 bool expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
313 bool expandDRotationImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
316 bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
319 bool expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
322 bool expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
325 bool expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
328 bool expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
331 bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
334 bool expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
337 bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
340 bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
343 bool expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
346 bool expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
349 bool expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
352 bool expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
442 bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
1872 bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, in processInstruction() argument
1880 Inst.setLoc(IDLoc); in processInstruction()
1904 return Error(IDLoc, "branch target out of range"); in processInstruction()
1907 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1934 return Error(IDLoc, "branch target out of range"); in processInstruction()
1937 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1950 return Error(IDLoc, "branch target out of range"); in processInstruction()
1952 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1963 return Error(IDLoc, "branch target out of range"); in processInstruction()
1965 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1974 return Error(IDLoc, "branch target out of range"); in processInstruction()
1976 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1987 return Error(IDLoc, "branch target out of range"); in processInstruction()
1989 return Error(IDLoc, "branch to misaligned address"); in processInstruction()
1998 Warning(IDLoc, "ssnop is deprecated for " + ISA + " and is equivalent to a " in processInstruction()
2018 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2022 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2035 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2038 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2062 Warning(IDLoc, "dividing zero by zero"); in processInstruction()
2064 Warning(IDLoc, "division by zero"); in processInstruction()
2090 Warning(IDLoc, "dividing zero by zero"); in processInstruction()
2092 Warning(IDLoc, "division by zero"); in processInstruction()
2110 warnIfNoMacro(IDLoc); in processInstruction()
2117 return Error(IDLoc, "jal doesn't support multiple symbols in PIC mode"); in processInstruction()
2124 !isGP64bit(), IDLoc, Out, STI)) in processInstruction()
2143 getContext(), IDLoc); in processInstruction()
2147 RelocJalrExpr, IDLoc, *STI); in processInstruction()
2162 expandMem9Inst(Inst, IDLoc, Out, STI, MCID.mayLoad()); in processInstruction()
2165 expandMem16Inst(Inst, IDLoc, Out, STI, MCID.mayLoad()); in processInstruction()
2191 IDLoc, STI); in processInstruction()
2210 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2214 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2220 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2223 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2228 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2231 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2236 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2240 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2245 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2250 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2255 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2258 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2264 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2267 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2274 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2277 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2284 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2287 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2292 return Error(IDLoc, "expected immediate operand kind"); in processInstruction()
2295 return Error(IDLoc, "immediate operand value out of range"); in processInstruction()
2300 return Error(IDLoc, "invalid operand for instruction"); in processInstruction()
2315 return Error(IDLoc, "invalid operand for instruction"); in processInstruction()
2327 tryExpandInstruction(Inst, IDLoc, Out, STI); in processInstruction()
2348 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, STI); in processInstruction()
2360 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst), IDLoc, in processInstruction()
2364 TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI); in processInstruction()
2366 Warning(IDLoc, "no .cprestore used in PIC mode"); in processInstruction()
2373 MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in tryExpandInstruction() argument
2379 return expandLoadImm(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2381 return expandLoadImm(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2390 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc, in tryExpandInstruction()
2403 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc, in tryExpandInstruction()
2409 return expandUncondBranchMMPseudo(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2413 return expandLoadStoreMultiple(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2417 return expandJalWithRegs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2422 return expandBranchImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2455 return expandCondBranches(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2460 return expandDivRem(Inst, IDLoc, Out, STI, false, true) ? MER_Fail in tryExpandInstruction()
2466 return expandDivRem(Inst, IDLoc, Out, STI, true, true) ? MER_Fail in tryExpandInstruction()
2472 return expandDivRem(Inst, IDLoc, Out, STI, false, false) ? MER_Fail in tryExpandInstruction()
2478 return expandDivRem(Inst, IDLoc, Out, STI, true, false) ? MER_Fail in tryExpandInstruction()
2481 return expandTrunc(Inst, false, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2484 return expandTrunc(Inst, true, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2487 return expandTrunc(Inst, true, true, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2491 return expandLoadSingleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2494 return expandLoadSingleImmToFPR(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2497 return expandLoadDoubleImmToGPR(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2500 return expandLoadDoubleImmToFPR(Inst, true, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2503 return expandLoadDoubleImmToFPR(Inst, false, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2507 return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2509 return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2511 return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2514 return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2517 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2520 return expandSge(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2525 return expandSgeImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2530 return expandSgtImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2533 return expandSle(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2538 return expandSleImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2544 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2550 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2560 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2572 return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail in tryExpandInstruction()
2578 return expandRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2581 return expandRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2584 return expandDRotation(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2587 return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2589 return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2592 return expandMulImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2595 return expandMulO(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2598 return expandMulOU(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2600 return expandDMULMacro(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2603 return expandLoadStoreDMacro(Inst, IDLoc, Out, STI, in tryExpandInstruction()
2608 return expandStoreDM1Macro(Inst, IDLoc, Out, STI) in tryExpandInstruction()
2612 return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2614 return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2616 return expandSne(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2618 return expandSneI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2628 return expandMXTRAlias(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2631 return expandSaaAddr(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; in tryExpandInstruction()
2635 bool MipsAsmParser::expandJalWithRegs(MCInst &Inst, SMLoc IDLoc, in expandJalWithRegs() argument
2642 JalrInst.setLoc(IDLoc); in expandJalWithRegs()
2675 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst), IDLoc, in expandJalWithRegs()
2700 bool IsAddress, SMLoc IDLoc, MCStreamer &Out, in loadImmediate() argument
2705 Error(IDLoc, "instruction requires a 64-bit architecture"); in loadImmediate()
2716 Error(IDLoc, "instruction requires a 32-bit immediate"); in loadImmediate()
2733 unsigned ATReg = getATReg(IDLoc); in loadImmediate()
2747 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2751 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
2758 TmpReg = getATReg(IDLoc); in loadImmediate()
2763 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2765 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2770 warnIfNoMacro(IDLoc); in loadImmediate()
2778 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2779 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2781 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2787 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2788 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in loadImmediate()
2790 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2792 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2796 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI); in loadImmediate()
2798 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI); in loadImmediate()
2800 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2806 Error(IDLoc, "instruction requires a 32-bit immediate"); in loadImmediate()
2816 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
2817 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
2820 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2825 warnIfNoMacro(IDLoc); in loadImmediate()
2833 IDLoc, Out, STI)) in loadImmediate()
2843 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); in loadImmediate()
2844 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI); in loadImmediate()
2854 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI); in loadImmediate()
2857 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2862 bool MipsAsmParser::expandLoadImm(MCInst &Inst, bool Is32BitImm, SMLoc IDLoc, in expandLoadImm() argument
2870 Is32BitImm, false, IDLoc, Out, STI)) in expandLoadImm()
2878 bool Is32BitAddress, SMLoc IDLoc, in expandLoadAddress() argument
2883 Warning(IDLoc, "la used to load 64-bit address"); in expandLoadAddress()
2890 Error(IDLoc, "instruction requires a 64-bit architecture"); in expandLoadAddress()
2896 Is32BitAddress, IDLoc, Out, STI); in expandLoadAddress()
2904 IDLoc, Out, STI); in expandLoadAddress()
2909 bool Is32BitSym, SMLoc IDLoc, in loadAndAddSymbolAddress() argument
2915 warnIfNoMacro(IDLoc); in loadAndAddSymbolAddress()
2920 Error(IDLoc, "expected relocatable expression"); in loadAndAddSymbolAddress()
2924 Error(IDLoc, "expected relocatable expression with only one symbol"); in loadAndAddSymbolAddress()
2948 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
2951 IDLoc, STI); in loadAndAddSymbolAddress()
2953 MCOperand::createExpr(CallLoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2958 MCOperand::createExpr(CallExpr), IDLoc, STI); in loadAndAddSymbolAddress()
2969 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
2993 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc, in loadAndAddSymbolAddress()
2996 IDLoc, STI); in loadAndAddSymbolAddress()
2998 MCOperand::createExpr(CallLoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3004 IDLoc, STI); in loadAndAddSymbolAddress()
3008 IDLoc, STI); in loadAndAddSymbolAddress()
3033 Error(IDLoc, "macro instruction uses large offset, which is not " in loadAndAddSymbolAddress()
3065 MCOperand::createExpr(GotExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3069 MCOperand::createExpr(LoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3073 IDLoc, STI); in loadAndAddSymbolAddress()
3101 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3111 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3114 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3115 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3117 IDLoc, STI); in loadAndAddSymbolAddress()
3118 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3120 IDLoc, STI); in loadAndAddSymbolAddress()
3121 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3124 } else if (canUseATReg() && !RdRegIsRsReg && DstReg != getATReg(IDLoc)) { in loadAndAddSymbolAddress()
3125 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3138 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3140 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3142 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3144 IDLoc, STI); in loadAndAddSymbolAddress()
3145 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI); in loadAndAddSymbolAddress()
3146 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI); in loadAndAddSymbolAddress()
3148 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3152 (canUseATReg() && DstReg == getATReg(IDLoc))) { in loadAndAddSymbolAddress()
3161 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc, in loadAndAddSymbolAddress()
3164 MCOperand::createExpr(HigherExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3165 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3167 MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3168 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI); in loadAndAddSymbolAddress()
3170 MCOperand::createExpr(LoExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3172 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3180 reportParseError(IDLoc, in loadAndAddSymbolAddress()
3200 unsigned ATReg = getATReg(IDLoc); in loadAndAddSymbolAddress()
3206 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in loadAndAddSymbolAddress()
3208 IDLoc, STI); in loadAndAddSymbolAddress()
3211 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3284 bool MipsAsmParser::emitPartialAddress(MipsTargetStreamer &TOut, SMLoc IDLoc, in emitPartialAddress() argument
3286 unsigned ATReg = getATReg(IDLoc); in emitPartialAddress()
3298 IDLoc, STI); in emitPartialAddress()
3301 IDLoc, STI); in emitPartialAddress()
3316 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI); in emitPartialAddress()
3327 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc, in emitPartialAddress()
3330 MCOperand::createExpr(HigherExpr), IDLoc, STI); in emitPartialAddress()
3331 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3333 IDLoc, STI); in emitPartialAddress()
3334 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI); in emitPartialAddress()
3358 bool MipsAsmParser::expandLoadSingleImmToGPR(MCInst &Inst, SMLoc IDLoc, in expandLoadSingleImmToGPR() argument
3370 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc, in expandLoadSingleImmToGPR()
3374 bool MipsAsmParser::expandLoadSingleImmToFPR(MCInst &Inst, SMLoc IDLoc, in expandLoadSingleImmToFPR() argument
3391 TmpReg = getATReg(IDLoc); in expandLoadSingleImmToFPR()
3398 true, false, IDLoc, Out, STI)) in expandLoadSingleImmToFPR()
3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3417 getStreamer().emitLabel(Sym, IDLoc); in expandLoadSingleImmToFPR()
3421 if (emitPartialAddress(TOut, IDLoc, Sym)) in expandLoadSingleImmToFPR()
3424 IDLoc, STI); in expandLoadSingleImmToFPR()
3428 bool MipsAsmParser::expandLoadDoubleImmToGPR(MCInst &Inst, SMLoc IDLoc, in expandLoadDoubleImmToGPR() argument
3444 IDLoc, Out, STI)) in expandLoadDoubleImmToGPR()
3448 IDLoc, Out, STI)) in expandLoadDoubleImmToGPR()
3452 IDLoc, Out, STI)) in expandLoadDoubleImmToGPR()
3469 getStreamer().emitLabel(Sym, IDLoc); in expandLoadDoubleImmToGPR()
3474 unsigned TmpReg = getATReg(IDLoc); in expandLoadDoubleImmToGPR()
3478 if (emitPartialAddress(TOut, IDLoc, Sym)) in expandLoadDoubleImmToGPR()
3482 MCOperand::createExpr(LoExpr), IDLoc, STI); in expandLoadDoubleImmToGPR()
3485 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3487 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI); in expandLoadDoubleImmToGPR()
3488 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI); in expandLoadDoubleImmToGPR()
3494 SMLoc IDLoc, MCStreamer &Out, in expandLoadDoubleImmToFPR() argument
3508 TmpReg = getATReg(IDLoc); in expandLoadDoubleImmToFPR()
3517 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc, in expandLoadDoubleImmToFPR()
3520 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3526 IDLoc, Out, STI)) in expandLoadDoubleImmToFPR()
3530 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3531 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3533 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3534 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3552 getStreamer().emitLabel(Sym, IDLoc); in expandLoadDoubleImmToFPR()
3557 if (emitPartialAddress(TOut, IDLoc, Sym)) in expandLoadDoubleImmToFPR()
3561 MCOperand::createExpr(LoExpr), IDLoc, STI); in expandLoadDoubleImmToFPR()
3566 bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, in expandUncondBranchMMPseudo() argument
3590 return Error(IDLoc, "branch target out of range"); in expandUncondBranchMMPseudo()
3592 return Error(IDLoc, "branch to misaligned address"); in expandUncondBranchMMPseudo()
3606 TOut.emitEmptyDelaySlot(true, IDLoc, STI); in expandUncondBranchMMPseudo()
3611 bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandBranchImm() argument
3651 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); in expandBranchImm()
3652 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3654 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc, in expandBranchImm()
3657 warnIfNoMacro(IDLoc); in expandBranchImm()
3659 unsigned ATReg = getATReg(IDLoc); in expandBranchImm()
3664 IDLoc, Out, STI)) in expandBranchImm()
3669 MCOperand::createExpr(MemOffsetOp.getExpr()), IDLoc, STI); in expandBranchImm()
3670 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); in expandBranchImm()
3672 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI); in expandBranchImm()
3677 void MipsAsmParser::expandMem16Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMem16Inst() argument
3705 TmpReg = getATReg(IDLoc); in expandMem16Inst()
3712 TOut.emitRRX(OpCode, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3714 TOut.emitRRRX(OpCode, DstReg, DstReg, TmpReg, Off, IDLoc, STI); in expandMem16Inst()
3731 IDLoc, Out, STI)) in expandMem16Inst()
3737 TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3752 Error(IDLoc, "expected relocatable expression"); in expandMem16Inst()
3756 Error(IDLoc, "expected relocatable expression with only one symbol"); in expandMem16Inst()
3761 !ABI.ArePtrs64bit(), IDLoc, Out, STI); in expandMem16Inst()
3781 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI); in expandMem16Inst()
3782 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI); in expandMem16Inst()
3783 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3784 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3785 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI); in expandMem16Inst()
3787 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3791 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in expandMem16Inst()
3793 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
3804 void MipsAsmParser::expandMem9Inst(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMem9Inst() argument
3832 TmpReg = getATReg(IDLoc); in expandMem9Inst()
3839 TOut.emitRRX(OpCode, DstReg, TmpReg, MCOperand::createImm(0), IDLoc, STI); in expandMem9Inst()
3842 IDLoc, STI); in expandMem9Inst()
3847 IDLoc, Out, STI); in expandMem9Inst()
3854 !ABI.ArePtrs64bit(), IDLoc, Out, STI); in expandMem9Inst()
3862 bool MipsAsmParser::expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc, in expandLoadStoreMultiple() argument
3891 bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc, in expandCondBranches() argument
3908 warnIfNoMacro(IDLoc); in expandCondBranches()
3911 TrgReg = getATReg(IDLoc); in expandCondBranches()
3969 false, IDLoc, Out, STI)) in expandCondBranches()
4034 IDLoc, STI); in expandCondBranches()
4039 IDLoc, STI); in expandCondBranches()
4040 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4045 IDLoc, STI); in expandCondBranches()
4046 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4051 IDLoc, STI); in expandCondBranches()
4056 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4063 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4064 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4088 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4089 Warning(IDLoc, "branch is always taken"); in expandCondBranches()
4107 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4115 MCOperand::createExpr(OffsetExpr), IDLoc, STI); in expandCondBranches()
4121 unsigned ATRegNum = getATReg(IDLoc); in expandCondBranches()
4126 warnIfNoMacro(IDLoc); in expandCondBranches()
4145 ReverseOrderSLT ? SrcReg : TrgReg, IDLoc, STI); in expandCondBranches()
4149 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc, in expandCondBranches()
4162 bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDivRem() argument
4167 warnIfNoMacro(IDLoc); in expandDivRem()
4216 unsigned ATReg = getATReg(IDLoc); in expandDivRem()
4222 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4224 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4229 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
4232 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI); in expandDivRem()
4235 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
4241 TOut.emitRR(DivOp, RsReg, ATReg, IDLoc, STI); in expandDivRem()
4242 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4254 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4257 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4264 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDivRem()
4274 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4279 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI); in expandDivRem()
4282 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI); in expandDivRem()
4285 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI); in expandDivRem()
4291 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4295 unsigned ATReg = getATReg(IDLoc); in expandDivRem()
4302 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
4310 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4313 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem()
4314 TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI); in expandDivRem()
4316 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI); in expandDivRem()
4320 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI); in expandDivRem()
4323 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI); in expandDivRem()
4324 TOut.emitNop(IDLoc, STI); in expandDivRem()
4325 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI); in expandDivRem()
4329 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4334 SMLoc IDLoc, MCStreamer &Out, in expandTrunc() argument
4347 unsigned ATReg = getATReg(IDLoc); in expandTrunc()
4350 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4351 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI); in expandTrunc()
4352 TOut.emitNop(IDLoc, STI); in expandTrunc()
4353 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI); in expandTrunc()
4354 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI); in expandTrunc()
4355 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI); in expandTrunc()
4356 TOut.emitNop(IDLoc, STI); in expandTrunc()
4359 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4360 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI); in expandTrunc()
4361 TOut.emitNop(IDLoc, STI); in expandTrunc()
4367 FirstReg, SecondReg, IDLoc, STI); in expandTrunc()
4372 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, in expandUlh() argument
4375 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUlh()
4392 warnIfNoMacro(IDLoc); in expandUlh()
4393 unsigned ATReg = getATReg(IDLoc); in expandUlh()
4400 IDLoc, Out, STI)) in expandUlh()
4416 FirstOffset, IDLoc, STI); in expandUlh()
4417 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); in expandUlh()
4418 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); in expandUlh()
4419 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUlh()
4424 bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandUsh() argument
4427 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUsh()
4442 warnIfNoMacro(IDLoc); in expandUsh()
4443 unsigned ATReg = getATReg(IDLoc); in expandUsh()
4450 IDLoc, Out, STI)) in expandUsh()
4460 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); in expandUsh()
4461 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4462 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); in expandUsh()
4463 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); in expandUsh()
4464 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); in expandUsh()
4465 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); in expandUsh()
4467 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); in expandUsh()
4468 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); in expandUsh()
4469 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); in expandUsh()
4475 bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandUxw() argument
4478 return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); in expandUxw()
4504 warnIfNoMacro(IDLoc); in expandUxw()
4505 TmpReg = getATReg(IDLoc); in expandUxw()
4512 IDLoc, Out, STI)) in expandUxw()
4521 TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI); in expandUxw()
4522 TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI); in expandUxw()
4525 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); in expandUxw()
4530 bool MipsAsmParser::expandSge(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSge() argument
4544 warnIfNoMacro(IDLoc); in expandSge()
4558 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4559 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSge()
4564 bool MipsAsmParser::expandSgeImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSgeImm() argument
4578 warnIfNoMacro(IDLoc); in expandSgeImm()
4598 TOut.emitRRI(OpImmCode, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSgeImm()
4599 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4610 false, IDLoc, Out, STI)) in expandSgeImm()
4613 TOut.emitRRR(OpRegCode, DstReg, SrcReg, ImmReg, IDLoc, STI); in expandSgeImm()
4614 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSgeImm()
4620 bool MipsAsmParser::expandSgtImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSgtImm() argument
4635 warnIfNoMacro(IDLoc); in expandSgtImm()
4658 false, IDLoc, Out, STI)) in expandSgtImm()
4662 TOut.emitRRR(OpCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSgtImm()
4667 bool MipsAsmParser::expandSle(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSle() argument
4681 warnIfNoMacro(IDLoc); in expandSle()
4695 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
4696 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSle()
4701 bool MipsAsmParser::expandSleImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSleImm() argument
4715 warnIfNoMacro(IDLoc); in expandSleImm()
4740 false, IDLoc, Out, STI)) in expandSleImm()
4743 TOut.emitRRR(OpRegCode, DstReg, ImmReg, SrcReg, IDLoc, STI); in expandSleImm()
4744 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI); in expandSleImm()
4749 bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc, in expandAliasImmediate() argument
4848 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI); in expandAliasImmediate()
4850 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI); in expandAliasImmediate()
4856 bool MipsAsmParser::expandRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandRotation() argument
4918 bool MipsAsmParser::expandRotationImm(MCInst &Inst, SMLoc IDLoc, in expandRotationImm() argument
4981 bool MipsAsmParser::expandDRotation(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDRotation() argument
5043 bool MipsAsmParser::expandDRotationImm(MCInst &Inst, SMLoc IDLoc, in expandDRotationImm() argument
5138 bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandAbs() argument
5144 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI); in expandAbs()
5146 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
5148 TOut.emitEmptyDelaySlot(false, IDLoc, STI); in expandAbs()
5149 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI); in expandAbs()
5154 bool MipsAsmParser::expandMulImm(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMulImm() argument
5162 ATReg = getATReg(IDLoc); in expandMulImm()
5166 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out, in expandMulImm()
5170 SrcReg, ATReg, IDLoc, STI); in expandMulImm()
5172 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulImm()
5177 bool MipsAsmParser::expandMulO(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMulO() argument
5190 SrcReg, TmpReg, IDLoc, STI); in expandMulO()
5192 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5195 DstReg, DstReg, 0x1F, IDLoc, STI); in expandMulO()
5197 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5200 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI); in expandMulO()
5207 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5209 TOut.emitNop(IDLoc, STI); in expandMulO()
5210 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulO()
5214 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulO()
5219 bool MipsAsmParser::expandMulOU(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMulOU() argument
5227 ATReg = getATReg(IDLoc); in expandMulOU()
5232 SrcReg, TmpReg, IDLoc, STI); in expandMulOU()
5234 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
5235 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandMulOU()
5237 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI); in expandMulOU()
5244 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); in expandMulOU()
5246 TOut.emitNop(IDLoc, STI); in expandMulOU()
5247 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI); in expandMulOU()
5255 bool MipsAsmParser::expandDMULMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandDMULMacro() argument
5262 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI); in expandDMULMacro()
5263 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI); in expandDMULMacro()
5273 bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, in expandLoadStoreDMacro() argument
5280 warnIfNoMacro(IDLoc); in expandLoadStoreDMacro()
5290 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandLoadStoreDMacro()
5305 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); in expandLoadStoreDMacro()
5306 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
5308 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandLoadStoreDMacro()
5309 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); in expandLoadStoreDMacro()
5321 bool MipsAsmParser::expandStoreDM1Macro(MCInst &Inst, SMLoc IDLoc, in expandStoreDM1Macro() argument
5327 warnIfNoMacro(IDLoc); in expandStoreDM1Macro()
5337 warnIfRegIndexIsAT(FirstReg, IDLoc); in expandStoreDM1Macro()
5352 TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); in expandStoreDM1Macro()
5353 TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); in expandStoreDM1Macro()
5358 bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSeq() argument
5371 warnIfNoMacro(IDLoc); in expandSeq()
5374 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5375 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeq()
5380 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI); in expandSeq()
5384 bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSeqI() argument
5397 warnIfNoMacro(IDLoc); in expandSeqI()
5400 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI); in expandSeqI()
5405 Warning(IDLoc, "comparison is always false"); in expandSeqI()
5407 DstReg, SrcReg, SrcReg, IDLoc, STI); in expandSeqI()
5420 unsigned ATReg = getATReg(IDLoc); in expandSeqI()
5424 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, in expandSeqI()
5428 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSeqI()
5429 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5433 TOut.emitRRI(Opc, DstReg, SrcReg, Imm, IDLoc, STI); in expandSeqI()
5434 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI); in expandSeqI()
5438 bool MipsAsmParser::expandSne(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSne() argument
5452 warnIfNoMacro(IDLoc); in expandSne()
5455 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSne()
5456 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSne()
5461 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI); in expandSne()
5465 bool MipsAsmParser::expandSneI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSneI() argument
5478 warnIfNoMacro(IDLoc); in expandSneI()
5481 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI); in expandSneI()
5486 Warning(IDLoc, "comparison is always true"); in expandSneI()
5487 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out, in expandSneI()
5502 TOut.emitRRI(Opc, DstReg, SrcReg, ImmValue, IDLoc, STI); in expandSneI()
5503 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5507 unsigned ATReg = getATReg(IDLoc); in expandSneI()
5512 false, IDLoc, Out, STI)) in expandSneI()
5515 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI); in expandSneI()
5516 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI); in expandSneI()
5656 bool MipsAsmParser::expandMXTRAlias(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandMXTRAlias() argument
5721 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc, in expandMXTRAlias()
5726 bool MipsAsmParser::expandSaaAddr(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, in expandSaaAddr() argument
5732 warnIfNoMacro(IDLoc); in expandSaaAddr()
5743 TOut.emitRR(Opcode, RtReg, BaseReg, IDLoc, STI); in expandSaaAddr()
5748 unsigned ATReg = getATReg(IDLoc); in expandSaaAddr()
5752 if (expandLoadAddress(ATReg, BaseReg, BaseOp, !isGP64bit(), IDLoc, Out, STI)) in expandSaaAddr()
5755 TOut.emitRR(Opcode, RtReg, ATReg, IDLoc, STI); in expandSaaAddr()
5925 bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, in MatchAndEmitInstruction() argument
5936 if (processInstruction(Inst, IDLoc, Out, STI)) in MatchAndEmitInstruction()
5940 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); in MatchAndEmitInstruction()
5943 SMLoc ErrorLoc = IDLoc; in MatchAndEmitInstruction()
5946 return Error(IDLoc, "too few operands for instruction"); in MatchAndEmitInstruction()
5950 ErrorLoc = IDLoc; in MatchAndEmitInstruction()
5956 return Error(IDLoc, in MatchAndEmitInstruction()
5959 return Error(IDLoc, "selector must be zero for pre-MIPS32 ISAs"); in MatchAndEmitInstruction()
5961 return Error(IDLoc, "invalid instruction"); in MatchAndEmitInstruction()
5963 return Error(IDLoc, "source and destination must be different"); in MatchAndEmitInstruction()
5965 return Error(IDLoc, "registers must be different"); in MatchAndEmitInstruction()
5967 return Error(IDLoc, "invalid operand ($zero) for instruction"); in MatchAndEmitInstruction()
5969 return Error(IDLoc, "source and destination must match"); in MatchAndEmitInstruction()
5971 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5974 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); in MatchAndEmitInstruction()
5976 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5979 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5982 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5985 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5988 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5991 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5994 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
5997 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6000 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6003 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6006 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6011 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6014 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6017 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6020 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6023 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6026 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6029 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6032 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6035 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6038 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6041 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6044 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6047 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6052 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6056 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6059 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6062 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6065 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6069 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6072 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6075 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6078 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6081 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6084 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6087 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6090 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6093 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6096 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()
6099 return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), in MatchAndEmitInstruction()