Lines Matching refs:RO
199 RegisterOperand RO> :
200 InstSE<(outs), (ins RO:$rs, opnd:$offset),
209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
211 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
224 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
266 class LLEBaseMM<string opstr, RegisterOperand RO> :
267 InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
274 class SCBaseMM<string opstr, RegisterOperand RO> :
275 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
282 class SCEBaseMM<string opstr, RegisterOperand RO> :
283 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
291 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
293 InstSE<(outs RO:$rt), (ins MO:$addr),
295 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
301 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
304 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
306 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
310 class AndImmMM16<string opstr, RegisterOperand RO,
312 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
315 class LogicRMM16<string opstr, RegisterOperand RO,
318 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
320 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
325 class NotMM16<string opstr, RegisterOperand RO> :
326 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
328 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
330 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
332 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
335 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
337 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
344 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
353 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
355 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
362 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
364 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
370 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
372 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
379 class AddImmUR2<string opstr, RegisterOperand RO> :
380 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
386 class AddImmUS5<string opstr, RegisterOperand RO> :
387 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
392 class AddImmUR1SP<string opstr, RegisterOperand RO> :
393 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
400 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
401 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
408 class MoveMM16<string opstr, RegisterOperand RO>
409 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
415 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
416 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
422 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
423 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
424 [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {
432 class JumpRegMM16<string opstr, RegisterOperand RO> :
433 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
451 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
452 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
460 class JumpRegCMM16<string opstr, RegisterOperand RO> :
461 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
475 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
476 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
492 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
493 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
497 RegisterOperand RO> :
498 InstSE<(outs), (ins RO:$rs, opnd:$offset),
502 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
504 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
512 class AddImmUPC<string opstr, RegisterOperand RO> :
513 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),