181   bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
329   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLogicalOp()  local
330   if (!ResultReg)  in emitLogicalOp()
333   emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);  in emitLogicalOp()
334   return ResultReg;  in emitLogicalOp()
345     unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in fastMaterializeAlloca()  local
347             ResultReg)  in fastMaterializeAlloca()
350     return ResultReg;  in fastMaterializeAlloca()
366   unsigned ResultReg = createResultReg(RC);  in materialize32BitInt()  local
370     emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);  in materialize32BitInt()
371     return ResultReg;  in materialize32BitInt()
373     emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);  in materialize32BitInt()
374     return ResultReg;  in materialize32BitInt()
382     emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);  in materialize32BitInt()
384     emitInst(Mips::LUi, ResultReg).addImm(Hi);  in materialize32BitInt()
386   return ResultReg;  in materialize32BitInt()
638 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {  in emitCmp()  argument
655     emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
661     emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);  in emitCmp()
665     emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
668     emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
673     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
679     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
683     emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);  in emitCmp()
686     emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);  in emitCmp()
691     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
697     emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);  in emitCmp()
747     emitInst(CondMovOpc, ResultReg)  in emitCmp()
757 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,  in emitLoad()  argument
765     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
769     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
773     ResultReg = createResultReg(&Mips::GPR32RegClass);  in emitLoad()
779     ResultReg = createResultReg(&Mips::FGR32RegClass);  in emitLoad()
785     ResultReg = createResultReg(&Mips::AFGR64RegClass);  in emitLoad()
793     emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());  in emitLoad()
803     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in emitLoad()
868   unsigned ResultReg;  in selectLogicalOp()  local
873     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
876     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
879     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
883   if (!ResultReg)  in selectLogicalOp()
886   updateValueMap(I, ResultReg);  in selectLogicalOp()
905   unsigned ResultReg;  in selectLoad()  local
906   if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))  in selectLoad()
908   updateValueMap(I, ResultReg);  in selectLoad()
986   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectCmp()  local
987   if (!emitCmp(ResultReg, CI))  in selectCmp()
989   updateValueMap(I, ResultReg);  in selectCmp()
1059   unsigned ResultReg = createResultReg(RC);  in selectSelect()  local
1062   if (!ResultReg || !TempReg)  in selectSelect()
1066   emitInst(CondMovOpc, ResultReg)  in selectSelect()
1068   updateValueMap(I, ResultReg);  in selectSelect()
1298     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));  in finishCall()  local
1299     if (!ResultReg)  in finishCall()
1303             ResultReg).addReg(RVLocs[0].getLocReg());  in finishCall()
1306     CLI.ResultReg = ResultReg;  in finishCall()
1470     unsigned ResultReg = createResultReg(Allocation[ArgNo].RC);  in fastLowerArguments()  local
1472             TII.get(TargetOpcode::COPY), ResultReg)  in fastLowerArguments()
1474     updateValueMap(&FormalArg, ResultReg);  in fastLowerArguments()
1822   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectIntExt()  local
1824   if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))  in selectIntExt()
1826   updateValueMap(I, ResultReg);  in selectIntExt()
1947   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectDivRem()  local
1948   if (!ResultReg)  in selectDivRem()
1954   emitInst(MFOpc, ResultReg);  in selectDivRem()
1956   updateValueMap(I, ResultReg);  in selectDivRem()
1966   unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);  in selectShift()  local
1967   if (!ResultReg)  in selectShift()
2007     emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);  in selectShift()
2008     updateValueMap(I, ResultReg);  in selectShift()
2030   emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);  in selectShift()
2031   updateValueMap(I, ResultReg);  in selectShift()
2134     unsigned ResultReg = createResultReg(RC);  in fastEmitInst_rr()  local
2138     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in fastEmitInst_rr()
2143     return ResultReg;  in fastEmitInst_rr()