Lines Matching refs:SrcVT
187 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
194 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
196 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
998 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPExt() local
1001 if (SrcVT != MVT::f32 || DestVT != MVT::f64) in selectFPExt()
1077 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true); in selectFPTrunc() local
1080 if (SrcVT != MVT::f64 || DestVT != MVT::f32) in selectFPTrunc()
1100 MVT DstVT, SrcVT; in selectFPToInt() local
1113 if (!isTypeLegal(SrcTy, SrcVT)) in selectFPToInt()
1116 if (SrcVT != MVT::f32 && SrcVT != MVT::f64) in selectFPToInt()
1127 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32; in selectFPToInt()
1211 MVT SrcVT = ArgVT; in processCallArgs() local
1212 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); in processCallArgs()
1219 MVT SrcVT = ArgVT; in processCallArgs() local
1220 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); in processCallArgs()
1783 EVT SrcVT, DestVT; in selectTrunc() local
1784 SrcVT = TLI.getValueType(DL, Op->getType(), true); in selectTrunc()
1787 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) in selectTrunc()
1820 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt() local
1824 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) in selectIntExt()
1830 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r1() argument
1833 switch (SrcVT.SimpleTy) { in emitIntSExt32r1()
1849 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt32r2() argument
1851 switch (SrcVT.SimpleTy) { in emitIntSExt32r2()
1864 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntSExt() argument
1869 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1870 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg); in emitIntSExt()
1873 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntZExt() argument
1877 switch (SrcVT.SimpleTy) { in emitIntZExt()
1895 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1902 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16))) in emitIntExt()
1905 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1906 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg); in emitIntExt()
1909 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, in emitIntExt() argument
1912 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); in emitIntExt()