Lines Matching refs:emitInst
210 MachineInstrBuilder emitInst(unsigned Opc) { in emitInst() function in __anon4be1e7190111::MipsFastISel
214 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) { in emitInst() function in __anon4be1e7190111::MipsFastISel
221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
381 emitInst(Mips::LUi, TmpReg).addImm(Hi); in materialize32BitInt()
382 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
384 emitInst(Mips::LUi, ResultReg).addImm(Hi); in materialize32BitInt()
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
405 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
422 emitInst(Mips::LW, DestReg) in materializeGV()
428 emitInst(Mips::ADDiu, TempReg) in materializeGV()
439 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
654 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
655 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
660 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); in emitCmp()
665 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
668 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
672 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
673 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
678 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
679 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
683 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
686 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
690 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
696 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
697 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); in emitCmp()
743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
745 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) in emitCmp()
747 emitInst(CondMovOpc, ResultReg) in emitCmp()
1011 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); in selectFPExt()
1065 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg); in selectSelect()
1066 emitInst(CondMovOpc, ResultReg) in selectSelect()
1091 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); in selectFPTrunc()
1130 emitInst(Opc, TempReg).addReg(SrcReg); in selectFPToInt()
1131 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
1150 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0); in processCallArgs()
1280 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0); in finishCall()
1558 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); in fastLowerCall()
1606 emitInst(Mips::WSBH, DestReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1616 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1617 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1618 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]); in fastLowerIntrinsicCall()
1619 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF); in fastLowerIntrinsicCall()
1626 emitInst(Mips::WSBH, TempReg).addReg(SrcReg); in fastLowerIntrinsicCall()
1627 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16); in fastLowerIntrinsicCall()
1638 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8); in fastLowerIntrinsicCall()
1639 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1640 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00); in fastLowerIntrinsicCall()
1641 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]); in fastLowerIntrinsicCall()
1643 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00); in fastLowerIntrinsicCall()
1644 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); in fastLowerIntrinsicCall()
1646 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); in fastLowerIntrinsicCall()
1647 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]); in fastLowerIntrinsicCall()
1648 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]); in fastLowerIntrinsicCall()
1772 MachineInstrBuilder MIB = emitInst(Mips::RetRA); in selectRet()
1844 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); in emitIntSExt32r1()
1845 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); in emitIntSExt32r1()
1855 emitInst(Mips::SEB, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1858 emitInst(Mips::SEH, DestReg).addReg(SrcReg); in emitIntSExt32r2()
1891 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm); in emitIntZExt()
1944 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg); in selectDivRem()
1945 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7); in selectDivRem()
1954 emitInst(MFOpc, ResultReg); in selectDivRem()
2007 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal); in selectShift()
2030 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg); in selectShift()
2117 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()